| Message ID | 20241122132044.30024-3-quic_yrangana@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Enable Inline crypto engine for QCS8300 | expand |
On 22.11.2024 2:20 PM, Yuvaraj Ranganathan wrote: > Add an ICE node to qcs8300 SoC description and enable it by adding a > phandle to the UFS node. > > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Getting *a review* does *not* mean I gave you a Reviewed-by tag. https://docs.kernel.org/process/submitting-patches.html#using-reported-by-tested-by-reviewed-by-suggested-by-and-fixes > Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > index 2c35f96c3f28..ab91c3b7bba6 100644 > --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > @@ -685,6 +685,7 @@ &mc_virt SLAVE_EBI1 0>, > <0 0>, > <0 0>, > <0 0>; > + qcom,ice = <&ice>; > status = "disabled"; > }; > > @@ -710,6 +711,13 @@ ufs_mem_phy: phy@1d87000 { > status = "disabled"; > }; > > + ice: crypto@1d88000 { > + compatible = "qcom,qcs8300-inline-crypto-engine", > + "qcom,inline-crypto-engine"; > + reg = <0x0 0x01d88000 0x0 0x18000>; > + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; > + }; Although this looks good now, so I'll allow you to keep it. I won't add it a second time here to avoid confusing the maintainer tools. Konrad
On 22/11/2024 14:20, Yuvaraj Ranganathan wrote: > Add an ICE node to qcs8300 SoC description and enable it by adding a > phandle to the UFS node. > > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> This did not happen. Provide a proof (lore link). Best regards, Krzysztof
Hi Krzysztof, Same mistake is done for this patch series as well. I sincerely apologize for the inconvenience. I will remove the tag in the next patch series. Thanks, Yuvaraj. On 11/22/2024 8:25 PM, Krzysztof Kozlowski wrote: > On 22/11/2024 14:20, Yuvaraj Ranganathan wrote: >> Add an ICE node to qcs8300 SoC description and enable it by adding a >> phandle to the UFS node. >> >> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > > This did not happen. Provide a proof (lore link). > > Best regards, > Krzysztof
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 2c35f96c3f28..ab91c3b7bba6 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -685,6 +685,7 @@ &mc_virt SLAVE_EBI1 0>, <0 0>, <0 0>, <0 0>; + qcom,ice = <&ice>; status = "disabled"; }; @@ -710,6 +711,13 @@ ufs_mem_phy: phy@1d87000 { status = "disabled"; }; + ice: crypto@1d88000 { + compatible = "qcom,qcs8300-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x01d88000 0x0 0x18000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>;