| Message ID | 20241126030159.72111-2-wangyuquan1236@phytium.com.cn |
|---|---|
| State | Superseded |
| Headers | show |
| Series | MdePkg/IndustryStandard: add definitions for CXL CEDT | expand |
On Tue, 26 Nov 2024 11:01:59 +0800 Yuquan Wang <wangyuquan1236@phytium.com.cn> wrote: > This adds #defines and struct typedefs for the various structure > types in the CXL Early Discovery Table (CEDT). > > Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn> Hi. One errata applies. See below. Otherwise, I've checked these against the r3.2 specification and they look correct. Some suggestions on places where comments might make that easier to establish when it comes to maximum sizing. Otherwise, with the errata fixed. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > diff --git a/MdePkg/Include/IndustryStandard/Cxl30.h b/MdePkg/Include/IndustryStandard/Cxl30.h > index 7a9a6d69405d..63e56aea8254 100644 > --- a/MdePkg/Include/IndustryStandard/Cxl30.h > +++ b/MdePkg/Include/IndustryStandard/Cxl30.h > @@ -45,6 +45,13 @@ > #define CXL_HDM_6_WAY_INTERLEAVING 0x9 > #define CXL_HDM_12_WAY_INTERLEAVING 0xA > > +/// > +/// "CEDT" CXL Early Discovery Table > +/// > +#define CEDT_TYPE_CFMWS 0x1 > +#define CEDT_TYPE_CXIMS 0x2 > +#define CEDT_TYPE_RDPAS 0x3 > + > // > // Ensure proper structure formats > // > @@ -311,6 +318,45 @@ typedef struct { > CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_STATUS TimeoutAndIsolationStatus; > } CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY_STRUCTURE; > > +/// > +/// Definition for CXL Fixed Memory Window Structure (CFMWS) > +/// > +typedef struct { > + CEDT_STRUCTURE Header; > + UINT32 Reserved; > + UINT64 BaseHpa; > + UINT64 WindowSize; > + UINT8 InterleaveMembers; Spec naming now at least is Encode Number of Interleave Ways. This name looses quite a bit of that. I'd use a longer name, perhaps EncodedInterleaveWays > + UINT8 InterleaveArithmetic; > + UINT16 Reserved1; > + UINT32 Granularity; > + UINT16 Restrictions; > + UINT16 QtgId; > + UINT32 TargetList[16]; Perhaps a comment on why 16 given it depends on decoded version of EncodedInterleaveWays. 16 is the current maximum. > +} CXL_FIXED_MEMORY_WINDOW_STRUCTURE; > + > +/// > +/// Definition for CXL XOR Interleave Math Structure (CXIMS) > +/// > +typedef struct { > + CEDT_STRUCTURE Header; > + UINT16 Reserved; > + UINT8 HBIG; > + UINT8 NIB; > + UINT64 XORMAPLIST[4]; Why 4? Number of entries depends on NIB. Add a comment if this is the effective maximum to refer to specific part of spec that says that. > +} CXL_XOR_INTERLEAVE_MATH_STRUCTURE; > + > +/// > +/// Definition for RCEC Downstream Port Association Structure (RDPAS) > +/// > +typedef struct { > + CEDT_STRUCTURE Header; > + UINT16 SegmentNumber; > + UINT16 Bdf; > + UINT8 ProtocolType; > + UINT64 BaseAddress; Always check the latest spec, which as of last week is 3.2 or any errata released in the meantime. There is an errata on this. Key is that in the 3.1 and before the fields don't fit. Offset of RCEC BDF is 06h, length 2 bytes, yet protocol type is in 07h so overlaps. Fix was to move protocol type later. > +} RCEC_DOWNSTREAM_PORT_ASSOCIATION_STRUCTURE; > + > #pragma pack() > > #endif
diff --git a/MdePkg/Include/IndustryStandard/Cxl20.h b/MdePkg/Include/IndustryStandard/Cxl20.h index 574f78688180..55ad8105a7bc 100755 --- a/MdePkg/Include/IndustryStandard/Cxl20.h +++ b/MdePkg/Include/IndustryStandard/Cxl20.h @@ -14,6 +14,7 @@ #define CXL20_H_ #include <IndustryStandard/Cxl11.h> +#include <IndustryStandard/Acpi.h> // // CXL DVSEC IDs @@ -102,6 +103,15 @@ #define CXL_MEM_DEVICE_MEDIA_STATUS_ERROR 0x2 #define CXL_MEM_DEVICE_MEDIA_STATUS_DISABLED 0x3 +/// +/// "CEDT" CXL Early Discovery Table +/// +#define CXL_EARLY_DISCOVERY_TABLE_SIGNATURE SIGNATURE_32 ('C', 'E', 'D', 'T') + +#define CXL_EARLY_DISCOVERY_TABLE_REVISION_01 0x1 + +#define CEDT_TYPE_CHBS 0x0 + // // Ensure proper structure formats // @@ -458,6 +468,34 @@ typedef union { UINT64 Uint64; } CXL_MEMORY_DEVICE_STATUS_REGISTER; +/// +/// CEDT header +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} CXL_EARLY_DISCOVERY_TABLE; + +/// +/// Node header definition shared by all CEDT structure types +/// +typedef struct { + UINT8 Type; + UINT8 Reserved; + UINT16 Length; +} CEDT_STRUCTURE; + +/// +/// Definition for CXL Host Bridge Structure (CHBS) +/// +typedef struct { + CEDT_STRUCTURE Header; + UINT32 Uid; + UINT32 CxlVersion; + UINT32 Reserved; + UINT64 Base; + UINT64 Length; +} CXL_HOST_BRIDGE_STRUCTURE; + #pragma pack() #endif diff --git a/MdePkg/Include/IndustryStandard/Cxl30.h b/MdePkg/Include/IndustryStandard/Cxl30.h index 7a9a6d69405d..63e56aea8254 100644 --- a/MdePkg/Include/IndustryStandard/Cxl30.h +++ b/MdePkg/Include/IndustryStandard/Cxl30.h @@ -45,6 +45,13 @@ #define CXL_HDM_6_WAY_INTERLEAVING 0x9 #define CXL_HDM_12_WAY_INTERLEAVING 0xA +/// +/// "CEDT" CXL Early Discovery Table +/// +#define CEDT_TYPE_CFMWS 0x1 +#define CEDT_TYPE_CXIMS 0x2 +#define CEDT_TYPE_RDPAS 0x3 + // // Ensure proper structure formats // @@ -311,6 +318,45 @@ typedef struct { CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_STATUS TimeoutAndIsolationStatus; } CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY_STRUCTURE; +/// +/// Definition for CXL Fixed Memory Window Structure (CFMWS) +/// +typedef struct { + CEDT_STRUCTURE Header; + UINT32 Reserved; + UINT64 BaseHpa; + UINT64 WindowSize; + UINT8 InterleaveMembers; + UINT8 InterleaveArithmetic; + UINT16 Reserved1; + UINT32 Granularity; + UINT16 Restrictions; + UINT16 QtgId; + UINT32 TargetList[16]; +} CXL_FIXED_MEMORY_WINDOW_STRUCTURE; + +/// +/// Definition for CXL XOR Interleave Math Structure (CXIMS) +/// +typedef struct { + CEDT_STRUCTURE Header; + UINT16 Reserved; + UINT8 HBIG; + UINT8 NIB; + UINT64 XORMAPLIST[4]; +} CXL_XOR_INTERLEAVE_MATH_STRUCTURE; + +/// +/// Definition for RCEC Downstream Port Association Structure (RDPAS) +/// +typedef struct { + CEDT_STRUCTURE Header; + UINT16 SegmentNumber; + UINT16 Bdf; + UINT8 ProtocolType; + UINT64 BaseAddress; +} RCEC_DOWNSTREAM_PORT_ASSOCIATION_STRUCTURE; + #pragma pack() #endif diff --git a/MdePkg/Include/IndustryStandard/Cxl31.h b/MdePkg/Include/IndustryStandard/Cxl31.h new file mode 100644 index 000000000000..4a62c971b045 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Cxl31.h @@ -0,0 +1,45 @@ +/** @file + CXL 3.1 definitions + + This file contains the register definitions and firmware interface based + on the Compute Express Link (CXL) Specification Revision 3.1. + + Copyright (c) 2024, Phytium Technology Co Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Reference(s): + - Compute Express Link (CXL) Specification Revision 3.1. + (https://computeexpresslink.org/cxl-specification/) + +**/ + +#ifndef CXL31_H_ +#define CXL31_H_ + +#include <IndustryStandard/Cxl30.h> + +/// +/// "CEDT" CXL Early Discovery Table +/// +#define CXL_EARLY_DISCOVERY_TABLE_REVISION_02 0x2 + +#define CEDT_TYPE_CSDS 0x4 + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// Definition for CXL System Description Structure (CSDS) +/// +typedef struct { + CEDT_STRUCTURE Header; + UINT16 Capabilities; + UINT16 Reserved; +} CXL_DOWNSTREAM_PORT_ASSOCIATION_STRUCTURE; + +#pragma pack() + +#endif
This adds #defines and struct typedefs for the various structure types in the CXL Early Discovery Table (CEDT). Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn> --- MdePkg/Include/IndustryStandard/Cxl20.h | 38 ++++++++++++++++++++ MdePkg/Include/IndustryStandard/Cxl30.h | 46 +++++++++++++++++++++++++ MdePkg/Include/IndustryStandard/Cxl31.h | 45 ++++++++++++++++++++++++ 3 files changed, 129 insertions(+) create mode 100644 MdePkg/Include/IndustryStandard/Cxl31.h