diff mbox series

[03/13] target/mips: Rename gen_move_low32() -> gen_move_low32_tl()

Message ID 20241126131546.66145-4-philmd@linaro.org (mailing list archive)
State New
Headers show
Series target/mips: Simplify some target_ulong registers to 32-bit | expand

Commit Message

Philippe Mathieu-Daudé Nov. 26, 2024, 1:15 p.m. UTC 
MIPS gen_move_low32() takes a target-specific TCGv argument.
Rename it as gen_move_low32_tl() to clarify, like other TCG
core helpers.

Mechanical change doing:

  $ sed -i -e 's/gen_move_low32/gen_move_low32_tl/' \
     $(git grep -l gen_move_low32)

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/translate.h              |  2 +-
 target/mips/tcg/mxu_translate.c          |  2 +-
 target/mips/tcg/translate.c              | 30 ++++++++++++------------
 target/mips/tcg/nanomips_translate.c.inc |  8 +++----
 4 files changed, 21 insertions(+), 21 deletions(-)

Comments

Richard Henderson Nov. 26, 2024, 1:51 p.m. UTC | #1 
On 11/26/24 07:15, Philippe Mathieu-Daudé wrote:
> MIPS gen_move_low32() takes a target-specific TCGv argument.
> Rename it as gen_move_low32_tl() to clarify, like other TCG
> core helpers.
> 
> Mechanical change doing:
> 
>    $ sed -i -e 's/gen_move_low32/gen_move_low32_tl/' \
>       $(git grep -l gen_move_low32)
> 
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 49f174d3617..6437180d891 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -153,7 +153,7 @@  void check_cp1_registers(DisasContext *ctx, int regs);
 void check_cop1x(DisasContext *ctx);
 
 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
-void gen_move_low32(TCGv ret, TCGv_i64 arg);
+void gen_move_low32_tl(TCGv ret, TCGv_i64 arg);
 void gen_move_high32(TCGv ret, TCGv_i64 arg);
 void gen_load_gpr_tl(TCGv t, int reg);
 void gen_store_gpr_tl(TCGv t, int reg);
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index 9525aebc053..94aa137cb25 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -4385,7 +4385,7 @@  static void gen_mxu_s32madd_sub(DisasContext *ctx, bool sub, bool uns)
         } else {
             tcg_gen_add_i64(t3, t3, t2);
         }
-        gen_move_low32(t1, t3);
+        gen_move_low32_tl(t1, t3);
         gen_move_high32(t0, t3);
 
         tcg_gen_mov_tl(cpu_HI[0], t0);
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 629846a596d..5e776136f09 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1452,7 +1452,7 @@  static target_long addr_add(DisasContext *ctx, target_long base,
 }
 
 /* Sign-extract the low 32-bits to a target_long.  */
-void gen_move_low32(TCGv ret, TCGv_i64 arg)
+void gen_move_low32_tl(TCGv ret, TCGv_i64 arg)
 {
 #if defined(TARGET_MIPS64)
     tcg_gen_ext32s_i64(ret, arg);
@@ -3341,7 +3341,7 @@  static void gen_muldiv(DisasContext *ctx, uint32_t opc,
             tcg_gen_mul_i64(t2, t2, t3);
             tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
             tcg_gen_add_i64(t2, t2, t3);
-            gen_move_low32(cpu_LO[acc], t2);
+            gen_move_low32_tl(cpu_LO[acc], t2);
             gen_move_high32(cpu_HI[acc], t2);
         }
         break;
@@ -3357,7 +3357,7 @@  static void gen_muldiv(DisasContext *ctx, uint32_t opc,
             tcg_gen_mul_i64(t2, t2, t3);
             tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
             tcg_gen_add_i64(t2, t2, t3);
-            gen_move_low32(cpu_LO[acc], t2);
+            gen_move_low32_tl(cpu_LO[acc], t2);
             gen_move_high32(cpu_HI[acc], t2);
         }
         break;
@@ -3371,7 +3371,7 @@  static void gen_muldiv(DisasContext *ctx, uint32_t opc,
             tcg_gen_mul_i64(t2, t2, t3);
             tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
             tcg_gen_sub_i64(t2, t3, t2);
-            gen_move_low32(cpu_LO[acc], t2);
+            gen_move_low32_tl(cpu_LO[acc], t2);
             gen_move_high32(cpu_HI[acc], t2);
         }
         break;
@@ -3387,7 +3387,7 @@  static void gen_muldiv(DisasContext *ctx, uint32_t opc,
             tcg_gen_mul_i64(t2, t2, t3);
             tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
             tcg_gen_sub_i64(t2, t3, t2);
-            gen_move_low32(cpu_LO[acc], t2);
+            gen_move_low32_tl(cpu_LO[acc], t2);
             gen_move_high32(cpu_HI[acc], t2);
         }
         break;
@@ -3482,10 +3482,10 @@  static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
             tcg_gen_mul_i64(t2, t2, t3);
             tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
             tcg_gen_add_i64(t2, t2, t3);
-            gen_move_low32(cpu_LO[acc], t2);
+            gen_move_low32_tl(cpu_LO[acc], t2);
             gen_move_high32(cpu_HI[acc], t2);
             if (rd) {
-                gen_move_low32(cpu_gpr[rd], t2);
+                gen_move_low32_tl(cpu_gpr[rd], t2);
             }
         }
         break;
@@ -3504,10 +3504,10 @@  static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
             tcg_gen_mul_i64(t2, t2, t3);
             tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
             tcg_gen_add_i64(t2, t2, t3);
-            gen_move_low32(cpu_LO[acc], t2);
+            gen_move_low32_tl(cpu_LO[acc], t2);
             gen_move_high32(cpu_HI[acc], t2);
             if (rd) {
-                gen_move_low32(cpu_gpr[rd], t2);
+                gen_move_low32_tl(cpu_gpr[rd], t2);
             }
         }
         break;
@@ -4787,7 +4787,7 @@  static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
                 TCGv_i64 t2 = tcg_temp_new_i64();
                 tcg_gen_concat_tl_i64(t2, t1, t0);
                 tcg_gen_shri_i64(t2, t2, 32 - bits);
-                gen_move_low32(cpu_gpr[rd], t2);
+                gen_move_low32_tl(cpu_gpr[rd], t2);
             }
             break;
 #if defined(TARGET_MIPS64)
@@ -4865,7 +4865,7 @@  static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off)
 #else
     tcg_gen_shri_i64(t0, t0, 32);
 #endif
-    gen_move_low32(arg, t0);
+    gen_move_low32_tl(arg, t0);
 }
 
 static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift)
@@ -4874,7 +4874,7 @@  static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift)
 
     tcg_gen_ld_i64(t0, tcg_env, off);
     tcg_gen_shri_i64(t0, t0, 32 + shift);
-    gen_move_low32(arg, t0);
+    gen_move_low32_tl(arg, t0);
 }
 
 static inline void gen_mfc0_load32(TCGv arg, target_ulong off)
@@ -5195,7 +5195,7 @@  static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
                     tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2);
                 }
 #endif
-                gen_move_low32(arg, tmp);
+                gen_move_low32_tl(arg, tmp);
             }
             register_name = "EntryLo0";
             break;
@@ -5252,7 +5252,7 @@  static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
                     tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2);
                 }
 #endif
-                gen_move_low32(arg, tmp);
+                gen_move_low32_tl(arg, tmp);
             }
             register_name = "EntryLo1";
             break;
@@ -5769,7 +5769,7 @@  static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             {
                 TCGv_i64 tmp = tcg_temp_new_i64();
                 tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUMIPSState, CP0_TagLo));
-                gen_move_low32(arg, tmp);
+                gen_move_low32_tl(arg, tmp);
             }
             register_name = "TagLo";
             break;
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 31a31c00979..5a4a64f3609 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -1816,7 +1816,7 @@  static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
                 tcg_gen_mul_i64(t2, t2, t3);
                 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
                 tcg_gen_add_i64(t2, t2, t3);
-                gen_move_low32(cpu_LO[acc], t2);
+                gen_move_low32_tl(cpu_LO[acc], t2);
                 gen_move_high32(cpu_HI[acc], t2);
             }
             break;
@@ -1871,7 +1871,7 @@  static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
                 tcg_gen_mul_i64(t2, t2, t3);
                 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
                 tcg_gen_add_i64(t2, t2, t3);
-                gen_move_low32(cpu_LO[acc], t2);
+                gen_move_low32_tl(cpu_LO[acc], t2);
                 gen_move_high32(cpu_HI[acc], t2);
             }
             break;
@@ -1932,7 +1932,7 @@  static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
                 tcg_gen_mul_i64(t2, t2, t3);
                 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
                 tcg_gen_sub_i64(t2, t3, t2);
-                gen_move_low32(cpu_LO[acc], t2);
+                gen_move_low32_tl(cpu_LO[acc], t2);
                 gen_move_high32(cpu_HI[acc], t2);
             }
             break;
@@ -1973,7 +1973,7 @@  static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
                 tcg_gen_mul_i64(t2, t2, t3);
                 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
                 tcg_gen_sub_i64(t2, t3, t2);
-                gen_move_low32(cpu_LO[acc], t2);
+                gen_move_low32_tl(cpu_LO[acc], t2);
                 gen_move_high32(cpu_HI[acc], t2);
             }
             break;