| Message ID | 20241128-adds-spmi-pmic-peripherals-for-qcs8300-v2-1-001c0bed7c67@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Adds SPMI bus, PMIC and peripherals for qcs8300-ride | expand |
On Thu, Nov 28, 2024 at 05:40:16PM +0800, Tingguo Cheng wrote: > Add the SPMI bus arbiter(Version:5.2.0) node for QCS8300 SoC > which connected with PMICs on QCS8300 boards. > > Signed-off-by: Tingguo Cheng <quic_tingguoc@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 2c35f96c3f289d5e2e57e0e30ef5e17cd1286188..03bf72d6ec5c9ec92f6f53df9253c8c5953e13c4 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -939,6 +939,28 @@ IPCC_MPROC_SIGNAL_GLINK_QMP #clock-cells = <0>; }; + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c440000 0x0 0x1100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x100000>, + <0x0 0x0e700000 0x0 0xa0000>, + <0x0 0x0c40a000 0x0 0x26000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + qcom,channel = <0>; + qcom,ee = <0>; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,qcs8300-tlmm"; reg = <0x0 0x0f100000 0x0 0x300000>;
Add the SPMI bus arbiter(Version:5.2.0) node for QCS8300 SoC which connected with PMICs on QCS8300 boards. Signed-off-by: Tingguo Cheng <quic_tingguoc@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)