| Message ID | 20241128-sm8750-dispcc-v1-1-120705a4015c@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | clk: qcom: sm8750: Add sm8750-dispcc clock controller | expand |
On Thu, Nov 28, 2024 at 04:07:59PM +0100, Krzysztof Kozlowski wrote: > Add bindings for the Qualcomm SM8750 Display Clock Controller (DISPCC). > Bindings are similar to existing SM8550 and SM8650 (same clock inputs), > but the clock hierarchy is quite different and these are not compatible > devices. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > .../bindings/clock/qcom,sm8550-dispcc.yaml | 4 +- > include/dt-bindings/clock/qcom,sm8750-dispcc.h | 112 +++++++++++++++++++++ > 2 files changed, 115 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml > index c57d55a9293c214c4c101902cdd9603074e2243d..30e4b46315752b93754ab2f946c684e13b06ab93 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml > @@ -12,11 +12,12 @@ maintainers: > > description: | > Qualcomm display clock control module provides the clocks, resets and power > - domains on SM8550. > + domains on SM8550, SM8650, SM8750 and few other platforms. > > See also: > - include/dt-bindings/clock/qcom,sm8550-dispcc.h > - include/dt-bindings/clock/qcom,sm8650-dispcc.h > + - include/dt-bindings/clock/qcom,sm8750-dispcc.h > - include/dt-bindings/clock/qcom,x1e80100-dispcc.h > > properties: > @@ -25,6 +26,7 @@ properties: > - qcom,sar2130p-dispcc > - qcom,sm8550-dispcc > - qcom,sm8650-dispcc > + - qcom,sm8750-dispcc > - qcom,x1e80100-dispcc > > clocks: > diff --git a/include/dt-bindings/clock/qcom,sm8750-dispcc.h b/include/dt-bindings/clock/qcom,sm8750-dispcc.h > new file mode 100644 > index 0000000000000000000000000000000000000000..dafb5069c96a0c3f83c15f3c61978e138baa886c > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,sm8750-dispcc.h > @@ -0,0 +1,112 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2022, The Linux Foundation. All rights reserved. This looks pretty questionable, how does something that was apparently announced last month have a 2022 copyright from the Linux Foundation? > + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > + * Copyright (c) 2024, Linaro Ltd. > + */ > + > +#ifndef _DT_BINDINGS_CLK_QCOM_SM8750_DISP_CC_H > +#define _DT_BINDINGS_CLK_QCOM_SM8750_DISP_CC_H > + > +/* DISP_CC clocks */ > +#define DISP_CC_ESYNC0_CLK 0 > +#define DISP_CC_ESYNC0_CLK_SRC 1 > +#define DISP_CC_ESYNC1_CLK 2 > +#define DISP_CC_ESYNC1_CLK_SRC 3 > +#define DISP_CC_MDSS_ACCU_SHIFT_CLK 4 > +#define DISP_CC_MDSS_AHB1_CLK 5 > +#define DISP_CC_MDSS_AHB_CLK 6 > +#define DISP_CC_MDSS_AHB_CLK_SRC 7 > +#define DISP_CC_MDSS_BYTE0_CLK 8 > +#define DISP_CC_MDSS_BYTE0_CLK_SRC 9 > +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 10 > +#define DISP_CC_MDSS_BYTE0_INTF_CLK 11 > +#define DISP_CC_MDSS_BYTE1_CLK 12 > +#define DISP_CC_MDSS_BYTE1_CLK_SRC 13 > +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 14 > +#define DISP_CC_MDSS_BYTE1_INTF_CLK 15 > +#define DISP_CC_MDSS_DPTX0_AUX_CLK 16 > +#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 17 > +#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 18 > +#define DISP_CC_MDSS_DPTX0_LINK_CLK 19 > +#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 20 > +#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 21 > +#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 22 > +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 23 > +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 24 > +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 25 > +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 26 > +#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 27 > +#define DISP_CC_MDSS_DPTX1_AUX_CLK 28 > +#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 29 > +#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 30 > +#define DISP_CC_MDSS_DPTX1_LINK_CLK 31 > +#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 32 > +#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 33 > +#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 34 > +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 35 > +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 36 > +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 37 > +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 38 > +#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 39 > +#define DISP_CC_MDSS_DPTX2_AUX_CLK 40 > +#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 41 > +#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 42 > +#define DISP_CC_MDSS_DPTX2_LINK_CLK 43 > +#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 44 > +#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 45 > +#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 46 > +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 47 > +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 48 > +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 49 > +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 50 > +#define DISP_CC_MDSS_DPTX3_AUX_CLK 51 > +#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 52 > +#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 53 > +#define DISP_CC_MDSS_DPTX3_LINK_CLK 54 > +#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 55 > +#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 56 > +#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 57 > +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 58 > +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 59 > +#define DISP_CC_MDSS_ESC0_CLK 60 > +#define DISP_CC_MDSS_ESC0_CLK_SRC 61 > +#define DISP_CC_MDSS_ESC1_CLK 62 > +#define DISP_CC_MDSS_ESC1_CLK_SRC 63 > +#define DISP_CC_MDSS_MDP1_CLK 64 > +#define DISP_CC_MDSS_MDP_CLK 65 > +#define DISP_CC_MDSS_MDP_CLK_SRC 66 > +#define DISP_CC_MDSS_MDP_LUT1_CLK 67 > +#define DISP_CC_MDSS_MDP_LUT_CLK 68 > +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 69 > +#define DISP_CC_MDSS_PCLK0_CLK 70 > +#define DISP_CC_MDSS_PCLK0_CLK_SRC 71 > +#define DISP_CC_MDSS_PCLK1_CLK 72 > +#define DISP_CC_MDSS_PCLK1_CLK_SRC 73 > +#define DISP_CC_MDSS_PCLK2_CLK 74 > +#define DISP_CC_MDSS_PCLK2_CLK_SRC 75 > +#define DISP_CC_MDSS_RSCC_AHB_CLK 76 > +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 77 > +#define DISP_CC_MDSS_VSYNC1_CLK 78 > +#define DISP_CC_MDSS_VSYNC_CLK 79 > +#define DISP_CC_MDSS_VSYNC_CLK_SRC 80 > +#define DISP_CC_OSC_CLK 81 > +#define DISP_CC_OSC_CLK_SRC 82 > +#define DISP_CC_PLL0 83 > +#define DISP_CC_PLL1 84 > +#define DISP_CC_PLL2 85 > +#define DISP_CC_SLEEP_CLK 86 > +#define DISP_CC_SLEEP_CLK_SRC 87 > +#define DISP_CC_XO_CLK 88 > +#define DISP_CC_XO_CLK_SRC 89 > + > +/* DISP_CC resets */ > +#define DISP_CC_MDSS_CORE_BCR 0 > +#define DISP_CC_MDSS_CORE_INT2_BCR 1 > +#define DISP_CC_MDSS_RSCC_BCR 2 > + > +/* DISP_CC GDSCR */ > +#define MDSS_GDSC 0 > +#define MDSS_INT2_GDSC 1 > + > +#endif > > -- > 2.43.0 >
On 28/11/2024 18:12, Conor Dooley wrote: >> >> clocks: >> diff --git a/include/dt-bindings/clock/qcom,sm8750-dispcc.h b/include/dt-bindings/clock/qcom,sm8750-dispcc.h >> new file mode 100644 >> index 0000000000000000000000000000000000000000..dafb5069c96a0c3f83c15f3c61978e138baa886c >> --- /dev/null >> +++ b/include/dt-bindings/clock/qcom,sm8750-dispcc.h >> @@ -0,0 +1,112 @@ >> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ >> +/* >> + * Copyright (c) 2022, The Linux Foundation. All rights reserved. > > This looks pretty questionable, how does something that was apparently > announced last month have a 2022 copyright from the Linux Foundation? > I copied the binding header from downstream sources, which had above copyrights. Rest of the changes - driver and bindings - are my work. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml index c57d55a9293c214c4c101902cdd9603074e2243d..30e4b46315752b93754ab2f946c684e13b06ab93 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml @@ -12,11 +12,12 @@ maintainers: description: | Qualcomm display clock control module provides the clocks, resets and power - domains on SM8550. + domains on SM8550, SM8650, SM8750 and few other platforms. See also: - include/dt-bindings/clock/qcom,sm8550-dispcc.h - include/dt-bindings/clock/qcom,sm8650-dispcc.h + - include/dt-bindings/clock/qcom,sm8750-dispcc.h - include/dt-bindings/clock/qcom,x1e80100-dispcc.h properties: @@ -25,6 +26,7 @@ properties: - qcom,sar2130p-dispcc - qcom,sm8550-dispcc - qcom,sm8650-dispcc + - qcom,sm8750-dispcc - qcom,x1e80100-dispcc clocks: diff --git a/include/dt-bindings/clock/qcom,sm8750-dispcc.h b/include/dt-bindings/clock/qcom,sm8750-dispcc.h new file mode 100644 index 0000000000000000000000000000000000000000..dafb5069c96a0c3f83c15f3c61978e138baa886c --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8750-dispcc.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_SM8750_DISP_CC_H +#define _DT_BINDINGS_CLK_QCOM_SM8750_DISP_CC_H + +/* DISP_CC clocks */ +#define DISP_CC_ESYNC0_CLK 0 +#define DISP_CC_ESYNC0_CLK_SRC 1 +#define DISP_CC_ESYNC1_CLK 2 +#define DISP_CC_ESYNC1_CLK_SRC 3 +#define DISP_CC_MDSS_ACCU_SHIFT_CLK 4 +#define DISP_CC_MDSS_AHB1_CLK 5 +#define DISP_CC_MDSS_AHB_CLK 6 +#define DISP_CC_MDSS_AHB_CLK_SRC 7 +#define DISP_CC_MDSS_BYTE0_CLK 8 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 9 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 10 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 11 +#define DISP_CC_MDSS_BYTE1_CLK 12 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 13 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 14 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 15 +#define DISP_CC_MDSS_DPTX0_AUX_CLK 16 +#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 17 +#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 18 +#define DISP_CC_MDSS_DPTX0_LINK_CLK 19 +#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 20 +#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 21 +#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 22 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 23 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 24 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 25 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 26 +#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 27 +#define DISP_CC_MDSS_DPTX1_AUX_CLK 28 +#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 29 +#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 30 +#define DISP_CC_MDSS_DPTX1_LINK_CLK 31 +#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 32 +#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 33 +#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 34 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 35 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 36 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 37 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 38 +#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 39 +#define DISP_CC_MDSS_DPTX2_AUX_CLK 40 +#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 41 +#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 42 +#define DISP_CC_MDSS_DPTX2_LINK_CLK 43 +#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 44 +#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 45 +#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 46 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 47 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 48 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 49 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 50 +#define DISP_CC_MDSS_DPTX3_AUX_CLK 51 +#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 52 +#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 53 +#define DISP_CC_MDSS_DPTX3_LINK_CLK 54 +#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 55 +#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 56 +#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 57 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 58 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 59 +#define DISP_CC_MDSS_ESC0_CLK 60 +#define DISP_CC_MDSS_ESC0_CLK_SRC 61 +#define DISP_CC_MDSS_ESC1_CLK 62 +#define DISP_CC_MDSS_ESC1_CLK_SRC 63 +#define DISP_CC_MDSS_MDP1_CLK 64 +#define DISP_CC_MDSS_MDP_CLK 65 +#define DISP_CC_MDSS_MDP_CLK_SRC 66 +#define DISP_CC_MDSS_MDP_LUT1_CLK 67 +#define DISP_CC_MDSS_MDP_LUT_CLK 68 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 69 +#define DISP_CC_MDSS_PCLK0_CLK 70 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 71 +#define DISP_CC_MDSS_PCLK1_CLK 72 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 73 +#define DISP_CC_MDSS_PCLK2_CLK 74 +#define DISP_CC_MDSS_PCLK2_CLK_SRC 75 +#define DISP_CC_MDSS_RSCC_AHB_CLK 76 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 77 +#define DISP_CC_MDSS_VSYNC1_CLK 78 +#define DISP_CC_MDSS_VSYNC_CLK 79 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 80 +#define DISP_CC_OSC_CLK 81 +#define DISP_CC_OSC_CLK_SRC 82 +#define DISP_CC_PLL0 83 +#define DISP_CC_PLL1 84 +#define DISP_CC_PLL2 85 +#define DISP_CC_SLEEP_CLK 86 +#define DISP_CC_SLEEP_CLK_SRC 87 +#define DISP_CC_XO_CLK 88 +#define DISP_CC_XO_CLK_SRC 89 + +/* DISP_CC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_CORE_INT2_BCR 1 +#define DISP_CC_MDSS_RSCC_BCR 2 + +/* DISP_CC GDSCR */ +#define MDSS_GDSC 0 +#define MDSS_INT2_GDSC 1 + +#endif
Add bindings for the Qualcomm SM8750 Display Clock Controller (DISPCC). Bindings are similar to existing SM8550 and SM8650 (same clock inputs), but the clock hierarchy is quite different and these are not compatible devices. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- .../bindings/clock/qcom,sm8550-dispcc.yaml | 4 +- include/dt-bindings/clock/qcom,sm8750-dispcc.h | 112 +++++++++++++++++++++ 2 files changed, 115 insertions(+), 1 deletion(-)