| Message ID | 20241127-gs101-phy-lanes-orientation-phy-v1-5-1b7fce24960b@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | USB31DRD phy updates for Google Tensor gs101 (orientation & DWC3 rpm) | expand |
Hi André, On Wed, 27 Nov 2024 at 10:58, André Draszik <andre.draszik@linaro.org> wrote: > > This code's intention is to configure lane0 and lane2 tunings, but for > lane2 there is a typo and it ends up tuning something else. > > Fix the typo, as it doesn't appear to make sense to apply different > tunings for lane0 vs lane2. > > The same typo appears to exist in the bootloader, hence we restore the > original value in the typo'd registers as well. This can be removed > once / if the bootloader is updated. > > Note that this is incorrect in the downstream driver as well - the > values had been copied from there. > > Signed-off-by: André Draszik <andre.draszik@linaro.org> > --- Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Validated that a super-speed USB link is established between Pixel 6 phone and my laptop with this patch applied and that adb works. regards, Peter
diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index ceae4b47cece..2a724d362c2d 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -1510,8 +1510,11 @@ static const struct exynos5_usbdrd_phy_tuning gs101_tunes_pipe3_preinit[] = { PHY_TUNING_ENTRY_PMA(0x09e0, -1, 0x00), PHY_TUNING_ENTRY_PMA(0x09e4, -1, 0x36), PHY_TUNING_ENTRY_PMA(0x1e7c, -1, 0x06), - PHY_TUNING_ENTRY_PMA(0x1e90, -1, 0x00), - PHY_TUNING_ENTRY_PMA(0x1e94, -1, 0x36), + PHY_TUNING_ENTRY_PMA(0x19e0, -1, 0x00), + PHY_TUNING_ENTRY_PMA(0x19e4, -1, 0x36), + /* fix bootloader bug */ + PHY_TUNING_ENTRY_PMA(0x1e90, -1, 0x02), + PHY_TUNING_ENTRY_PMA(0x1e94, -1, 0x0b), /* improve LVCC */ PHY_TUNING_ENTRY_PMA(0x08f0, -1, 0x30), PHY_TUNING_ENTRY_PMA(0x18f0, -1, 0x30),
This code's intention is to configure lane0 and lane2 tunings, but for lane2 there is a typo and it ends up tuning something else. Fix the typo, as it doesn't appear to make sense to apply different tunings for lane0 vs lane2. The same typo appears to exist in the bootloader, hence we restore the original value in the typo'd registers as well. This can be removed once / if the bootloader is updated. Note that this is incorrect in the downstream driver as well - the values had been copied from there. Signed-off-by: André Draszik <andre.draszik@linaro.org> --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)