[12/15] KVM: x86: Track possible passthrough MSRs in kvm_x86_ops

Message ID	20241127201929.4005605-13-aaronlewis@google.com (mailing list archive)
State	New, archived
Headers	show Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03233203718 for <kvm@vger.kernel.org>; Wed, 27 Nov 2024 20:20:08 +0000 (UTC) Date: Wed, 27 Nov 2024 20:19:26 +0000 In-Reply-To: <20241127201929.4005605-1-aaronlewis@google.com> Precedence: bulk Mime-Version: 1.0 References: <20241127201929.4005605-1-aaronlewis@google.com> Message-ID: <20241127201929.4005605-13-aaronlewis@google.com> Subject: [PATCH 12/15] KVM: x86: Track possible passthrough MSRs in kvm_x86_ops From: Aaron Lewis <aaronlewis@google.com> To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, jmattson@google.com, seanjc@google.com, Aaron Lewis <aaronlewis@google.com> Content-Type: text/plain; charset="UTF-8"
Series	Unify MSR intercepts in x86 \| expand [00/15] Unify MSR intercepts in x86 [01/15] KVM: x86: Use non-atomic bit ops to manipulate "shadow" MSR intercepts [02/15] KVM: SVM: Use non-atomic bit ops to manipulate MSR interception bitmaps [03/15] KVM: SVM: Invert the polarity of the "shadow" MSR interception bitmaps [04/15] KVM: SVM: Track MSRPM as "unsigned long", not "u32" [05/15] KVM: x86: SVM: Adopt VMX style MSR intercepts in SVM [06/15] KVM: SVM: Disable intercepts for all direct access MSRs on MSR filter changes [07/15] KVM: SVM: Delete old SVM MSR management code [08/15] KVM: SVM: Pass through GHCB MSR if and only if VM is SEV-ES [09/15] KVM: SVM: Drop "always" flag from list of possible passthrough MSRs [10/15] KVM: SVM: Don't "NULL terminate" the list of possible passthrough MSRs [11/15] KVM: VMX: Make list of possible passthrough MSRs "const" [12/15] KVM: x86: Track possible passthrough MSRs in kvm_x86_ops [13/15] KVM: x86: Move ownership of passthrough MSR "shadow" to common x86 [14/15] KVM: x86: Hoist SVM MSR intercepts to common x86 code [15/15] KVM: x86: Hoist VMX MSR intercepts to common x86 code

diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 3e8afc82ae2fb..7e9fee4d36cc2 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1817,6 +1817,9 @@ struct kvm_x86_ops { int (*enable_l2_tlb_flush)(struct kvm_vcpu *vcpu); void (*migrate_timers)(struct kvm_vcpu *vcpu); + + const u32 * const possible_passthrough_msrs; + const u32 nr_possible_passthrough_msrs; void (*msr_filter_changed)(struct kvm_vcpu *vcpu); int (*complete_emulated_msr)(struct kvm_vcpu *vcpu, int err); diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 4e30efe90c541..23e6515bb7904 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -755,18 +755,6 @@ static void clr_dr_intercepts(struct vcpu_svm *svm) recalc_intercepts(svm); } -static int direct_access_msr_slot(u32 msr) -{ - u32 i; - - for (i = 0; i < ARRAY_SIZE(direct_access_msrs); i++) { - if (direct_access_msrs[i] == msr) - return i; - } - - return -ENOENT; -} - static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) { u8 bit_write; @@ -832,7 +820,7 @@ void svm_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type) struct vcpu_svm *svm = to_svm(vcpu); int slot; - slot = direct_access_msr_slot(msr); + slot = kvm_passthrough_msr_slot(msr); WARN_ON(slot == -ENOENT); if (slot >= 0) { /* Set the shadow bitmaps to the desired intercept states */ @@ -871,7 +859,7 @@ void svm_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type) struct vcpu_svm *svm = to_svm(vcpu); int slot; - slot = direct_access_msr_slot(msr); + slot = kvm_passthrough_msr_slot(msr); WARN_ON(slot == -ENOENT); if (slot >= 0) { /* Set the shadow bitmaps to the desired intercept states */ @@ -5165,6 +5153,8 @@ static struct kvm_x86_ops svm_x86_ops __initdata = { .apic_init_signal_blocked = svm_apic_init_signal_blocked, + .possible_passthrough_msrs = direct_access_msrs, + .nr_possible_passthrough_msrs = ARRAY_SIZE(direct_access_msrs), .msr_filter_changed = svm_msr_filter_changed, .complete_emulated_msr = svm_complete_emulated_msr, diff --git a/arch/x86/kvm/vmx/main.c b/arch/x86/kvm/vmx/main.c index 92d35cc6cd15d..6d52693b0fd6c 100644 --- a/arch/x86/kvm/vmx/main.c +++ b/arch/x86/kvm/vmx/main.c @@ -7,6 +7,62 @@ #include "pmu.h" #include "posted_intr.h" +/* + * List of MSRs that can be directly passed to the guest. + * In addition to these x2apic, PT and LBR MSRs are handled specially. + */ +static const u32 vmx_possible_passthrough_msrs[] = { + MSR_IA32_SPEC_CTRL, + MSR_IA32_PRED_CMD, + MSR_IA32_FLUSH_CMD, + MSR_IA32_TSC, +#ifdef CONFIG_X86_64 + MSR_FS_BASE, + MSR_GS_BASE, + MSR_KERNEL_GS_BASE, + MSR_IA32_XFD, + MSR_IA32_XFD_ERR, +#endif + MSR_IA32_SYSENTER_CS, + MSR_IA32_SYSENTER_ESP, + MSR_IA32_SYSENTER_EIP, + MSR_CORE_C1_RES, + MSR_CORE_C3_RESIDENCY, + MSR_CORE_C6_RESIDENCY, + MSR_CORE_C7_RESIDENCY, +}; + +void vmx_msr_filter_changed(struct kvm_vcpu *vcpu) +{ + struct vcpu_vmx *vmx = to_vmx(vcpu); + u32 i; + + if (!cpu_has_vmx_msr_bitmap()) + return; + + /* + * Redo intercept permissions for MSRs that KVM is passing through to + * the guest. Disabling interception will check the new MSR filter and + * ensure that KVM enables interception if usersepace wants to filter + * the MSR. MSRs that KVM is already intercepting don't need to be + * refreshed since KVM is going to intercept them regardless of what + * userspace wants. + */ + for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) { + u32 msr = vmx_possible_passthrough_msrs[i]; + + if (!test_bit(i, vmx->shadow_msr_intercept.read)) + vmx_disable_intercept_for_msr(vcpu, msr, MSR_TYPE_R); + + if (!test_bit(i, vmx->shadow_msr_intercept.write)) + vmx_disable_intercept_for_msr(vcpu, msr, MSR_TYPE_W); + } + + /* PT MSRs can be passed through iff PT is exposed to the guest. */ + if (vmx_pt_mode_is_host_guest()) + pt_update_intercept_for_msr(vcpu); +} + #define VMX_REQUIRED_APICV_INHIBITS \ (BIT(APICV_INHIBIT_REASON_DISABLED) | \ BIT(APICV_INHIBIT_REASON_ABSENT) | \ @@ -152,6 +208,8 @@ struct kvm_x86_ops vt_x86_ops __initdata = { .apic_init_signal_blocked = vmx_apic_init_signal_blocked, .migrate_timers = vmx_migrate_timers, + .possible_passthrough_msrs = vmx_possible_passthrough_msrs, + .nr_possible_passthrough_msrs = ARRAY_SIZE(vmx_possible_passthrough_msrs), .msr_filter_changed = vmx_msr_filter_changed, .complete_emulated_msr = kvm_complete_insn_gp, diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index bc64e7cc02704..1c2c0c06f3d35 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -163,31 +163,6 @@ module_param(allow_smaller_maxphyaddr, bool, S_IRUGO); RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \ RTIT_STATUS_BYTECNT)) -/* - * List of MSRs that can be directly passed to the guest. - * In addition to these x2apic, PT and LBR MSRs are handled specially. - */ -static const u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = { - MSR_IA32_SPEC_CTRL, - MSR_IA32_PRED_CMD, - MSR_IA32_FLUSH_CMD, - MSR_IA32_TSC, -#ifdef CONFIG_X86_64 - MSR_FS_BASE, - MSR_GS_BASE, - MSR_KERNEL_GS_BASE, - MSR_IA32_XFD, - MSR_IA32_XFD_ERR, -#endif - MSR_IA32_SYSENTER_CS, - MSR_IA32_SYSENTER_ESP, - MSR_IA32_SYSENTER_EIP, - MSR_CORE_C1_RES, - MSR_CORE_C3_RESIDENCY, - MSR_CORE_C6_RESIDENCY, - MSR_CORE_C7_RESIDENCY, -}; - /* * These 2 parameters are used to config the controls for Pause-Loop Exiting: * ple_gap: upper bound on the amount of time between two successive @@ -669,7 +644,7 @@ static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) static int vmx_get_passthrough_msr_slot(u32 msr) { - int i; + int r; switch (msr) { case 0x800 ... 0x8ff: @@ -692,13 +667,10 @@ static int vmx_get_passthrough_msr_slot(u32 msr) return -ENOENT; } - for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) { - if (vmx_possible_passthrough_msrs[i] == msr) - return i; - } + r = kvm_passthrough_msr_slot(msr); - WARN(1, "Invalid MSR %x, please adapt vmx_possible_passthrough_msrs[]", msr); - return -ENOENT; + WARN(!r, "Invalid MSR %x, please adapt vmx_possible_passthrough_msrs[]", msr); + return r; } struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr) @@ -4145,37 +4117,6 @@ void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu) } } -void vmx_msr_filter_changed(struct kvm_vcpu *vcpu) -{ - struct vcpu_vmx *vmx = to_vmx(vcpu); - u32 i; - - if (!cpu_has_vmx_msr_bitmap()) - return; - - /* - * Redo intercept permissions for MSRs that KVM is passing through to - * the guest. Disabling interception will check the new MSR filter and - * ensure that KVM enables interception if usersepace wants to filter - * the MSR. MSRs that KVM is already intercepting don't need to be - * refreshed since KVM is going to intercept them regardless of what - * userspace wants. - */ - for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) { - u32 msr = vmx_possible_passthrough_msrs[i]; - - if (!test_bit(i, vmx->shadow_msr_intercept.read)) - vmx_disable_intercept_for_msr(vcpu, msr, MSR_TYPE_R); - - if (!test_bit(i, vmx->shadow_msr_intercept.write)) - vmx_disable_intercept_for_msr(vcpu, msr, MSR_TYPE_W); - } - - /* PT MSRs can be passed through iff PT is exposed to the guest. */ - if (vmx_pt_mode_is_host_guest()) - pt_update_intercept_for_msr(vcpu); -} - static inline void kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, int pi_vec) { diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 8637bc0010965..20b6cce793af5 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1806,6 +1806,19 @@ bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) } EXPORT_SYMBOL_GPL(kvm_msr_allowed); +int kvm_passthrough_msr_slot(u32 msr) +{ + u32 i; + + for (i = 0; i < kvm_x86_ops.nr_possible_passthrough_msrs; i++) { + if (kvm_x86_ops.possible_passthrough_msrs[i] == msr) + return i; + } + + return -ENOENT; +} +EXPORT_SYMBOL_GPL(kvm_passthrough_msr_slot); + /* * Write @data into the MSR specified by @index. Select MSR specific fault * checks are bypassed if @host_initiated is %true. diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index ec623d23d13d2..208f0698c64e2 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -555,6 +555,7 @@ int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, struct x86_exception *e); int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva); bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type); +int kvm_passthrough_msr_slot(u32 msr); enum kvm_msr_access { MSR_TYPE_R = BIT(0),

[12/15] KVM: x86: Track possible passthrough MSRs in kvm_x86_ops

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