| Message ID | 20241205-dp_mst-v1-41-f8618d42a99a@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | drm/msm/dp: Add MST support for MSM chipsets | expand |
On Thu, Dec 05, 2024 at 08:32:12PM -0800, Abhinav Kumar wrote: > Use msm_dp_get_mst_intf_id() to get the intf id for the DP MST > controller as the intf_id is unique for each MST stream of each > DP controller. > > Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 25 ++++++++++++++++++++----- > 1 file changed, 20 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index 83de7564e2c1fe14fcf8c4f82335cafc937e1b99..ce2f0fa8ebb1efd1a229a99543593965dbccd752 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -2512,17 +2512,23 @@ static int dpu_encoder_virt_add_phys_encs( > > static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, > struct dpu_kms *dpu_kms, > - struct msm_display_info *disp_info) > + struct msm_display_info *disp_info, > + int drm_enc_mode) No need to, use dpu_enc->base.encoder_type > { > int ret = 0; > int i = 0; > struct dpu_enc_phys_init_params phys_params; > + unsigned int intf_id; > + struct msm_drm_private *priv; > + struct drm_encoder *drm_enc; > > if (!dpu_enc) { > DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL); > return -EINVAL; > } > > + drm_enc = &dpu_enc->base; > + priv = drm_enc->dev->dev_private; > dpu_enc->cur_master = NULL; > > memset(&phys_params, 0, sizeof(phys_params)); > @@ -2559,9 +2565,18 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, > DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n", > i, controller_id, phys_params.split_role); > > - phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm, > - disp_info->intf_type, > - controller_id); > + if (drm_enc_mode == DRM_MODE_ENCODER_DPMST) { > + intf_id = msm_dp_get_mst_intf_id(priv->dp[controller_id], > + disp_info->stream_id); > + DPU_DEBUG("intf_id %d for disp_info->stream_id = %d\n", intf_id, > + disp_info->stream_id); > + phys_params.hw_intf = dpu_rm_get_intf(&dpu_kms->rm, intf_id); > + > + } else { > + phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm, > + disp_info->intf_type, > + controller_id); > + } > > if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX) > phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id); > @@ -2662,7 +2677,7 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev, > mutex_init(&dpu_enc->enc_lock); > mutex_init(&dpu_enc->rc_lock); > > - ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info); > + ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info, drm_enc_mode); > if (ret) { > DPU_ERROR("failed to setup encoder\n"); > return ERR_PTR(-ENOMEM); > > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 83de7564e2c1fe14fcf8c4f82335cafc937e1b99..ce2f0fa8ebb1efd1a229a99543593965dbccd752 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2512,17 +2512,23 @@ static int dpu_encoder_virt_add_phys_encs( static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, struct dpu_kms *dpu_kms, - struct msm_display_info *disp_info) + struct msm_display_info *disp_info, + int drm_enc_mode) { int ret = 0; int i = 0; struct dpu_enc_phys_init_params phys_params; + unsigned int intf_id; + struct msm_drm_private *priv; + struct drm_encoder *drm_enc; if (!dpu_enc) { DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL); return -EINVAL; } + drm_enc = &dpu_enc->base; + priv = drm_enc->dev->dev_private; dpu_enc->cur_master = NULL; memset(&phys_params, 0, sizeof(phys_params)); @@ -2559,9 +2565,18 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n", i, controller_id, phys_params.split_role); - phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm, - disp_info->intf_type, - controller_id); + if (drm_enc_mode == DRM_MODE_ENCODER_DPMST) { + intf_id = msm_dp_get_mst_intf_id(priv->dp[controller_id], + disp_info->stream_id); + DPU_DEBUG("intf_id %d for disp_info->stream_id = %d\n", intf_id, + disp_info->stream_id); + phys_params.hw_intf = dpu_rm_get_intf(&dpu_kms->rm, intf_id); + + } else { + phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm, + disp_info->intf_type, + controller_id); + } if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX) phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id); @@ -2662,7 +2677,7 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev, mutex_init(&dpu_enc->enc_lock); mutex_init(&dpu_enc->rc_lock); - ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info); + ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info, drm_enc_mode); if (ret) { DPU_ERROR("failed to setup encoder\n"); return ERR_PTR(-ENOMEM);
Use msm_dp_get_mst_intf_id() to get the intf id for the DP MST controller as the intf_id is unique for each MST stream of each DP controller. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-)