| Message ID | 20241206-sm8750_videocc-v1-1-5da6e7eea2bd@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add the support for SM8750 Video clock controller | expand |
On Fri, Dec 06, 2024 at 11:07:11PM +0530, Taniya Das wrote: > Extend the support for mem ops implementation to handle the > sequence of enable/disable of the memories for the invert > logic. This mostly duplicates the patch contents. Instead commit message should explain what is the "invert logic" and why it is relevant. > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- > drivers/clk/qcom/clk-branch.c | 14 +++++++++++--- > drivers/clk/qcom/clk-branch.h | 4 ++++ > 2 files changed, 15 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c > index 229480c5b075a0e70dc05b1cb15b88d29fd475ce..6caded8688c081e51ad0649f9c2f82919e461668 100644 > --- a/drivers/clk/qcom/clk-branch.c > +++ b/drivers/clk/qcom/clk-branch.c > @@ -142,8 +142,12 @@ static int clk_branch2_mem_enable(struct clk_hw *hw) > u32 val; > int ret; > > - regmap_update_bits(branch.clkr.regmap, mem_br->mem_enable_reg, > - mem_br->mem_enable_ack_mask, mem_br->mem_enable_ack_mask); > + if (mem_br->mem_enable_invert) > + regmap_update_bits(branch.clkr.regmap, mem_br->mem_enable_reg, > + mem_br->mem_enable_mask, 0); > + else > + regmap_update_bits(branch.clkr.regmap, mem_br->mem_enable_reg, > + mem_br->mem_enable_ack_mask, mem_br->mem_enable_ack_mask); > > ret = regmap_read_poll_timeout(branch.clkr.regmap, mem_br->mem_ack_reg, > val, val & mem_br->mem_enable_ack_mask, 0, 200); > @@ -159,7 +163,11 @@ static void clk_branch2_mem_disable(struct clk_hw *hw) > { > struct clk_mem_branch *mem_br = to_clk_mem_branch(hw); > > - regmap_update_bits(mem_br->branch.clkr.regmap, mem_br->mem_enable_reg, > + if (mem_br->mem_enable_invert) > + regmap_update_bits(mem_br->branch.clkr.regmap, mem_br->mem_enable_reg, > + mem_br->mem_enable_mask, mem_br->mem_enable_mask); > + else > + regmap_update_bits(mem_br->branch.clkr.regmap, mem_br->mem_enable_reg, > mem_br->mem_enable_ack_mask, 0); > > return clk_branch2_disable(hw); > diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h > index 292756435f53648640717734af198442a315272e..6bc2ba2b5350554005b7f0c84f933580b7582fc7 100644 > --- a/drivers/clk/qcom/clk-branch.h > +++ b/drivers/clk/qcom/clk-branch.h > @@ -44,6 +44,8 @@ struct clk_branch { > * @mem_enable_reg: branch clock memory gating register > * @mem_ack_reg: branch clock memory ack register > * @mem_enable_ack_mask: branch clock memory enable and ack field in @mem_ack_reg > + * @mem_enable_mask: branch clock memory enable mask > + * @mem_enable_invert: branch clock memory enable and disable has invert logic > * @branch: branch clock gating handle > * > * Clock which can gate its memories. > @@ -52,6 +54,8 @@ struct clk_mem_branch { > u32 mem_enable_reg; > u32 mem_ack_reg; > u32 mem_enable_ack_mask; > + u32 mem_enable_mask; > + bool mem_enable_invert; > struct clk_branch branch; > }; > > > -- > 2.45.2 >
diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index 229480c5b075a0e70dc05b1cb15b88d29fd475ce..6caded8688c081e51ad0649f9c2f82919e461668 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -142,8 +142,12 @@ static int clk_branch2_mem_enable(struct clk_hw *hw) u32 val; int ret; - regmap_update_bits(branch.clkr.regmap, mem_br->mem_enable_reg, - mem_br->mem_enable_ack_mask, mem_br->mem_enable_ack_mask); + if (mem_br->mem_enable_invert) + regmap_update_bits(branch.clkr.regmap, mem_br->mem_enable_reg, + mem_br->mem_enable_mask, 0); + else + regmap_update_bits(branch.clkr.regmap, mem_br->mem_enable_reg, + mem_br->mem_enable_ack_mask, mem_br->mem_enable_ack_mask); ret = regmap_read_poll_timeout(branch.clkr.regmap, mem_br->mem_ack_reg, val, val & mem_br->mem_enable_ack_mask, 0, 200); @@ -159,7 +163,11 @@ static void clk_branch2_mem_disable(struct clk_hw *hw) { struct clk_mem_branch *mem_br = to_clk_mem_branch(hw); - regmap_update_bits(mem_br->branch.clkr.regmap, mem_br->mem_enable_reg, + if (mem_br->mem_enable_invert) + regmap_update_bits(mem_br->branch.clkr.regmap, mem_br->mem_enable_reg, + mem_br->mem_enable_mask, mem_br->mem_enable_mask); + else + regmap_update_bits(mem_br->branch.clkr.regmap, mem_br->mem_enable_reg, mem_br->mem_enable_ack_mask, 0); return clk_branch2_disable(hw); diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 292756435f53648640717734af198442a315272e..6bc2ba2b5350554005b7f0c84f933580b7582fc7 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -44,6 +44,8 @@ struct clk_branch { * @mem_enable_reg: branch clock memory gating register * @mem_ack_reg: branch clock memory ack register * @mem_enable_ack_mask: branch clock memory enable and ack field in @mem_ack_reg + * @mem_enable_mask: branch clock memory enable mask + * @mem_enable_invert: branch clock memory enable and disable has invert logic * @branch: branch clock gating handle * * Clock which can gate its memories. @@ -52,6 +54,8 @@ struct clk_mem_branch { u32 mem_enable_reg; u32 mem_ack_reg; u32 mem_enable_ack_mask; + u32 mem_enable_mask; + bool mem_enable_invert; struct clk_branch branch; };
Extend the support for mem ops implementation to handle the sequence of enable/disable of the memories for the invert logic. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> --- drivers/clk/qcom/clk-branch.c | 14 +++++++++++--- drivers/clk/qcom/clk-branch.h | 4 ++++ 2 files changed, 15 insertions(+), 3 deletions(-)