| Message ID | 20241210160452.2427965-11-peter.maydell@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: Pull TLBI insns out to their own source file | expand |
On 12/10/24 10:04, Peter Maydell wrote: > We currently register the tlbi_el2_cp_reginfo[] TLBI insns if EL2 is > implemented, or if EL3 and v8 is implemented. This is a copy of the > logic used for el2_cp_reginfo[], but for the specific case of the > TLBI insns we can simplify it. This is because we do not need the > "if EL2 does not exist but EL3 does then EL2 registers should exist > and be RAZ/WI" handling here: all our cpregs are for instructions, > which UNDEF when EL3 exists and EL2 does not. > > Simplify the condition down to just "if EL2 exists". > This is not a behaviour change because: > * for AArch64 insns we marked them with ARM_CP_EL3_NO_EL2_UNDEF, > which meant that define_arm_cp_regs() would ignore them if > EL2 wasn't present > * for AArch32 insns, the .access = PL2_W meant that if EL2 > was not present the only way to get at them was from AArch32 > EL3; but we have no CPUs which have ARM_FEATURE_V8 but > start in AArch32 > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c index d20d32624da..0f67294edc4 100644 --- a/target/arm/tcg/tlb-insns.c +++ b/target/arm/tcg/tlb-insns.c @@ -1246,9 +1246,7 @@ void define_tlb_insn_regs(ARMCPU *cpu) * ops (i.e. matching the condition for el2_cp_reginfo[] in * helper.c), but we will be able to simplify this later. */ - if (arm_feature(env, ARM_FEATURE_EL2) - || (arm_feature(env, ARM_FEATURE_EL3) - && arm_feature(env, ARM_FEATURE_V8))) { + if (arm_feature(env, ARM_FEATURE_EL2)) { define_arm_cp_regs(cpu, tlbi_el2_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_EL3)) {
We currently register the tlbi_el2_cp_reginfo[] TLBI insns if EL2 is implemented, or if EL3 and v8 is implemented. This is a copy of the logic used for el2_cp_reginfo[], but for the specific case of the TLBI insns we can simplify it. This is because we do not need the "if EL2 does not exist but EL3 does then EL2 registers should exist and be RAZ/WI" handling here: all our cpregs are for instructions, which UNDEF when EL3 exists and EL2 does not. Simplify the condition down to just "if EL2 exists". This is not a behaviour change because: * for AArch64 insns we marked them with ARM_CP_EL3_NO_EL2_UNDEF, which meant that define_arm_cp_regs() would ignore them if EL2 wasn't present * for AArch32 insns, the .access = PL2_W meant that if EL2 was not present the only way to get at them was from AArch32 EL3; but we have no CPUs which have ARM_FEATURE_V8 but start in AArch32 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/tlb-insns.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)