Message ID | 20241210170953.2936724-3-claudiu.beznea.uj@bp.renesas.com (mailing list archive) |
---|---|
State | Accepted |
Delegated to: | Geert Uytterhoeven |
Headers | show |
Series | Add audio support for the Renesas RZ/G3S SoC | expand |
Quoting Claudiu (2024-12-10 09:09:31) > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > There are some differences b/w 5L35023 and 5P35023 Versa3 clock > generator variants but the same driver could be used with minimal > adjustments. The identified differences are PLL2 Fvco, the clock sel > bit for SE2 clock and different default values for some registers. > > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- Applied to clk-next
diff --git a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml index 42b6f80613f3..162d38035188 100644 --- a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml @@ -31,6 +31,7 @@ description: | properties: compatible: enum: + - renesas,5l35023 - renesas,5p35023 reg: