diff mbox series

[v2,7/8] drm/mediatek: Add programming flow for unsupported subsys ID hardware

Message ID 20241211032256.28494-8-jason-jh.lin@mediatek.com (mailing list archive)
State New
Headers show
Series Add GCE support for MT8196 | expand

Commit Message

Jason-JH.Lin Dec. 11, 2024, 3:22 a.m. UTC 
To support hardware without subsys IDs on new SoCs, add a programming
flow that checks whether the subsys ID is valid. If the subsys ID is
invalid, the flow will call 2 alternative CMDQ APIs:
cmdq_pkt_assign() and cmdq_pkt_write_s_value() to achieve the same
functionality.

Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 34 ++++++++++++++++++++-----
 1 file changed, 28 insertions(+), 6 deletions(-)

Comments

CK Hu (胡俊光) Dec. 11, 2024, 3:46 a.m. UTC | #1 
Hi, Jason:

On Wed, 2024-12-11 at 11:22 +0800, Jason-JH.Lin wrote:
> To support hardware without subsys IDs on new SoCs, add a programming
> flow that checks whether the subsys ID is valid. If the subsys ID is
> invalid, the flow will call 2 alternative CMDQ APIs:
> cmdq_pkt_assign() and cmdq_pkt_write_s_value() to achieve the same
> functionality.
> 
> Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 34 ++++++++++++++++++++-----
>  1 file changed, 28 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> index edc6417639e6..0792c895526f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> @@ -66,14 +66,38 @@ struct mtk_ddp_comp_dev {
>  	struct cmdq_client_reg cmdq_reg;
>  };
>  
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> +static void mtk_ddp_write_cmdq_pkt(struct cmdq_pkt *cmdq_pkt, struct cmdq_client_reg *cmdq_reg,
> +				   unsigned int offset, unsigned int value, unsigned int mask)

Drop this function.

> +{
> +	struct cmdq_client *cl = (struct cmdq_client *)cmdq_pkt->cl;
> +
> +	offset += cmdq_reg->offset;
> +
> +	if (cmdq_subsys_is_valid(cl->chan, cmdq_reg->subsys)) {
> +		if (mask == GENMASK(31, 0))
> +			cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, offset, value);
> +		else
> +			cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, offset, value, mask);
> +	} else {
> +		/* only MMIO access, no need to check mminfro_offset */
> +		cmdq_pkt_assign(cmdq_pkt, 0, CMDQ_ADDR_HIGH(cmdq_reg->pa_base));
> +		if (mask == GENMASK(31, 0))
> +			cmdq_pkt_write_s_value(cmdq_pkt, 0, CMDQ_ADDR_LOW(offset), value);
> +		else
> +			cmdq_pkt_write_s_mask_value(cmdq_pkt, 0, CMDQ_ADDR_LOW(offset),
> +						    value, mask);
> +	}
> +}
> +#endif
> +
>  void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
>  		   struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
>  		   unsigned int offset)
>  {
>  #if IS_REACHABLE(CONFIG_MTK_CMDQ)
>  	if (cmdq_pkt)
> -		cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
> -			       cmdq_reg->offset + offset, value);
> +		mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, GENMASK(31, 0));

/* only MMIO access, no need to check mminfro_offset */
cmdq_pkt_assign(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_HIGH(cmdq_reg->pa_base));
cmdq_pkt_write_s_value(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_LOW(offset), value);

>  	else
>  #endif
>  		writel(value, regs + offset);
> @@ -85,8 +109,7 @@ void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
>  {
>  #if IS_REACHABLE(CONFIG_MTK_CMDQ)
>  	if (cmdq_pkt)
> -		cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
> -			       cmdq_reg->offset + offset, value);
> +		mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, GENMASK(31, 0));

/* only MMIO access, no need to check mminfro_offset */
cmdq_pkt_assign(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_HIGH(cmdq_reg->pa_base));
cmdq_pkt_write_s_value(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_LOW(offset), value);

>  	else
>  #endif
>  		writel_relaxed(value, regs + offset);
> @@ -98,8 +121,7 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
>  {
>  #if IS_REACHABLE(CONFIG_MTK_CMDQ)
>  	if (cmdq_pkt) {
> -		cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
> -				    cmdq_reg->offset + offset, value, mask);
> +		mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, mask);

/* only MMIO access, no need to check mminfro_offset */
cmdq_pkt_assign(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_HIGH(cmdq_reg->pa_base));
cmdq_pkt_write_s_mask_value(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_LOW(offset),
			    value, mask);

CMDQ_XXXREG_0 is defined in cmdq header file.

Regards,
CK

>  	} else {
>  #endif
>  		u32 tmp = readl(regs + offset);
CK Hu (胡俊光) Dec. 11, 2024, 4:04 a.m. UTC | #2 
On Wed, 2024-12-11 at 11:46 +0800, CK Hu wrote:
> Hi, Jason:
> 
> On Wed, 2024-12-11 at 11:22 +0800, Jason-JH.Lin wrote:
> > To support hardware without subsys IDs on new SoCs, add a programming
> > flow that checks whether the subsys ID is valid. If the subsys ID is
> > invalid, the flow will call 2 alternative CMDQ APIs:
> > cmdq_pkt_assign() and cmdq_pkt_write_s_value() to achieve the same
> > functionality.
> > 
> > Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 34 ++++++++++++++++++++-----
> >  1 file changed, 28 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > index edc6417639e6..0792c895526f 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > @@ -66,14 +66,38 @@ struct mtk_ddp_comp_dev {
> >  	struct cmdq_client_reg cmdq_reg;
> >  };
> >  
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > +static void mtk_ddp_write_cmdq_pkt(struct cmdq_pkt *cmdq_pkt, struct cmdq_client_reg *cmdq_reg,
> > +				   unsigned int offset, unsigned int value, unsigned int mask)
> 
> Drop this function.

Sorry, it seems cmdq_subsys_is_valid() is used to check the SoC support new API or not.
But I would try to find out a way not to always check using new API or not.

Regards,
CK

> 
> > +{
> > +	struct cmdq_client *cl = (struct cmdq_client *)cmdq_pkt->cl;
> > +
> > +	offset += cmdq_reg->offset;
> > +
> > +	if (cmdq_subsys_is_valid(cl->chan, cmdq_reg->subsys)) {
> > +		if (mask == GENMASK(31, 0))
> > +			cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, offset, value);
> > +		else
> > +			cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, offset, value, mask);
> > +	} else {
> > +		/* only MMIO access, no need to check mminfro_offset */
> > +		cmdq_pkt_assign(cmdq_pkt, 0, CMDQ_ADDR_HIGH(cmdq_reg->pa_base));
> > +		if (mask == GENMASK(31, 0))
> > +			cmdq_pkt_write_s_value(cmdq_pkt, 0, CMDQ_ADDR_LOW(offset), value);
> > +		else
> > +			cmdq_pkt_write_s_mask_value(cmdq_pkt, 0, CMDQ_ADDR_LOW(offset),
> > +						    value, mask);
> > +	}
> > +}
> > +#endif
> > +
> >  void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
> >  		   struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
> >  		   unsigned int offset)
> >  {
> >  #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> >  	if (cmdq_pkt)
> > -		cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
> > -			       cmdq_reg->offset + offset, value);
> > +		mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, GENMASK(31, 0));
> 
> /* only MMIO access, no need to check mminfro_offset */
> cmdq_pkt_assign(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_HIGH(cmdq_reg->pa_base));
> cmdq_pkt_write_s_value(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_LOW(offset), value);
> 
> >  	else
> >  #endif
> >  		writel(value, regs + offset);
> > @@ -85,8 +109,7 @@ void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
> >  {
> >  #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> >  	if (cmdq_pkt)
> > -		cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
> > -			       cmdq_reg->offset + offset, value);
> > +		mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, GENMASK(31, 0));
> 
> /* only MMIO access, no need to check mminfro_offset */
> cmdq_pkt_assign(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_HIGH(cmdq_reg->pa_base));
> cmdq_pkt_write_s_value(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_LOW(offset), value);
> 
> >  	else
> >  #endif
> >  		writel_relaxed(value, regs + offset);
> > @@ -98,8 +121,7 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
> >  {
> >  #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> >  	if (cmdq_pkt) {
> > -		cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
> > -				    cmdq_reg->offset + offset, value, mask);
> > +		mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, mask);
> 
> /* only MMIO access, no need to check mminfro_offset */
> cmdq_pkt_assign(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_HIGH(cmdq_reg->pa_base));
> cmdq_pkt_write_s_mask_value(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_LOW(offset),
> 			    value, mask);
> 
> CMDQ_XXXREG_0 is defined in cmdq header file.
> 
> Regards,
> CK
> 
> >  	} else {
> >  #endif
> >  		u32 tmp = readl(regs + offset);
>
Jason-JH.Lin Dec. 12, 2024, 3:48 a.m. UTC | #3 
Hi CK,

Thanks for the reviews.

On Wed, 2024-12-11 at 04:04 +0000, CK Hu (胡俊光) wrote:
> On Wed, 2024-12-11 at 11:46 +0800, CK Hu wrote:
> > Hi, Jason:
> > 
> > On Wed, 2024-12-11 at 11:22 +0800, Jason-JH.Lin wrote:
> > > To support hardware without subsys IDs on new SoCs, add a
> > > programming
> > > flow that checks whether the subsys ID is valid. If the subsys ID
> > > is
> > > invalid, the flow will call 2 alternative CMDQ APIs:
> > > cmdq_pkt_assign() and cmdq_pkt_write_s_value() to achieve the
> > > same
> > > functionality.
> > > 
> > > Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
> > > ---
> > >  drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 34
> > > ++++++++++++++++++++-----
> > >  1 file changed, 28 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > > index edc6417639e6..0792c895526f 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > > @@ -66,14 +66,38 @@ struct mtk_ddp_comp_dev {
> > >  	struct cmdq_client_reg cmdq_reg;
> > >  };
> > >  
> > > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > > +static void mtk_ddp_write_cmdq_pkt(struct cmdq_pkt *cmdq_pkt,
> > > struct cmdq_client_reg *cmdq_reg,
> > > +				   unsigned int offset, unsigned int
> > > value, unsigned int mask)
> > 
> > Drop this function.
> 
> Sorry, it seems cmdq_subsys_is_valid() is used to check the SoC
> support new API or not.
> But I would try to find out a way not to always check using new API
> or not.
> 

OK, I can help you  test it, if you have any idea for this.

I'll use `cl->chan, cmdq_reg->subsys == INVALID_SUBSYS` instead of
calling `cmdq_subsys_is_valid()` to avoid function calls.

> Regards,
> CK
> 
> > 
> > > +{
> > > +	struct cmdq_client *cl = (struct cmdq_client *)cmdq_pkt->cl;
> > > +
> > > +	offset += cmdq_reg->offset;
> > > +
> > > +	if (cmdq_subsys_is_valid(cl->chan, cmdq_reg->subsys)) {
> > > +		if (mask == GENMASK(31, 0))
> > > +			cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
> > > offset, value);
> > > +		else
> > > +			cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, 
> > > offset, value, mask);
> > > +	} else {
> > > +		/* only MMIO access, no need to check mminfro_offset */
> > > +		cmdq_pkt_assign(cmdq_pkt, 0, CMDQ_ADDR_HIGH(cmdq_reg-
> > > >pa_base));
> > > +		if (mask == GENMASK(31, 0))
> > > +			cmdq_pkt_write_s_value(cmdq_pkt, 0,
> > > CMDQ_ADDR_LOW(offset), value);
> > > +		else
> > > +			cmdq_pkt_write_s_mask_value(cmdq_pkt, 0,
> > > CMDQ_ADDR_LOW(offset),
> > > +						    value, mask);
> > > +	}
> > > +}
> > > +#endif

[snip]

> > >  	else
> > >  #endif
> > >  		writel_relaxed(value, regs + offset);
> > > @@ -98,8 +121,7 @@ void mtk_ddp_write_mask(struct cmdq_pkt
> > > *cmdq_pkt, unsigned int value,
> > >  {
> > >  #if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > >  	if (cmdq_pkt) {
> > > -		cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
> > > -				    cmdq_reg->offset + offset, value,
> > > mask);
> > > +		mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset,
> > > value, mask);
> > 
> > /* only MMIO access, no need to check mminfro_offset */
> > cmdq_pkt_assign(cmdq_pkt, CMDQ_XXXREG_0, CMDQ_ADDR_HIGH(cmdq_reg-
> > >pa_base));
> > cmdq_pkt_write_s_mask_value(cmdq_pkt, CMDQ_XXXREG_0,
> > CMDQ_ADDR_LOW(offset),
> > 			    value, mask);
> > 
> > CMDQ_XXXREG_0 is defined in cmdq header file.
> > 

OK, I'll use CMDQ_THR_SPR_IDX0 instead.

Regards,
Jason-JH.Lin

> > Regards,
> > CK
diff mbox series

Patch

diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index edc6417639e6..0792c895526f 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -66,14 +66,38 @@  struct mtk_ddp_comp_dev {
 	struct cmdq_client_reg cmdq_reg;
 };
 
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+static void mtk_ddp_write_cmdq_pkt(struct cmdq_pkt *cmdq_pkt, struct cmdq_client_reg *cmdq_reg,
+				   unsigned int offset, unsigned int value, unsigned int mask)
+{
+	struct cmdq_client *cl = (struct cmdq_client *)cmdq_pkt->cl;
+
+	offset += cmdq_reg->offset;
+
+	if (cmdq_subsys_is_valid(cl->chan, cmdq_reg->subsys)) {
+		if (mask == GENMASK(31, 0))
+			cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, offset, value);
+		else
+			cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, offset, value, mask);
+	} else {
+		/* only MMIO access, no need to check mminfro_offset */
+		cmdq_pkt_assign(cmdq_pkt, 0, CMDQ_ADDR_HIGH(cmdq_reg->pa_base));
+		if (mask == GENMASK(31, 0))
+			cmdq_pkt_write_s_value(cmdq_pkt, 0, CMDQ_ADDR_LOW(offset), value);
+		else
+			cmdq_pkt_write_s_mask_value(cmdq_pkt, 0, CMDQ_ADDR_LOW(offset),
+						    value, mask);
+	}
+}
+#endif
+
 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
 		   struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
 		   unsigned int offset)
 {
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	if (cmdq_pkt)
-		cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
-			       cmdq_reg->offset + offset, value);
+		mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, GENMASK(31, 0));
 	else
 #endif
 		writel(value, regs + offset);
@@ -85,8 +109,7 @@  void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
 {
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	if (cmdq_pkt)
-		cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
-			       cmdq_reg->offset + offset, value);
+		mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, GENMASK(31, 0));
 	else
 #endif
 		writel_relaxed(value, regs + offset);
@@ -98,8 +121,7 @@  void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
 {
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	if (cmdq_pkt) {
-		cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
-				    cmdq_reg->offset + offset, value, mask);
+		mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, mask);
 	} else {
 #endif
 		u32 tmp = readl(regs + offset);