| Message ID | 20241206111337.726244-15-claudiu.beznea.uj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 78f2c089d0797fbf677a415aeeba8061b442027b |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | iio: adc: rzg2l_adc: Add support for RZ/G3S | expand |
Hi Claudiu, On Fri, Dec 6, 2024 at 12:14 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Add the device tree node for the ADC IP available on the Renesas RZ/G3S > SoC. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi > @@ -87,6 +87,59 @@ rtc: rtc@1004ec00 { > status = "disabled"; > }; > > + adc: adc@10058000 { > + compatible = "renesas,r9a08g045-adc"; > + reg = <0 0x10058000 0 0x400>; Table 5.1 ("Detailed Address Space") says the size is 4 KiB. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.14, with the above fixed. Gr{oetje,eeting}s, Geert
Hi, Geert, On 11.12.2024 15:27, Geert Uytterhoeven wrote: > Hi Claudiu, > > On Fri, Dec 6, 2024 at 12:14 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> >> Add the device tree node for the ADC IP available on the Renesas RZ/G3S >> SoC. >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Thanks for your patch! > >> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi >> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi >> @@ -87,6 +87,59 @@ rtc: rtc@1004ec00 { >> status = "disabled"; >> }; >> >> + adc: adc@10058000 { >> + compatible = "renesas,r9a08g045-adc"; >> + reg = <0 0x10058000 0 0x400>; > > Table 5.1 ("Detailed Address Space") says the size is 4 KiB. > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > i.e. will queue in renesas-devel for v6.14, with the above fixed. Thank you! > > Gr{oetje,eeting}s, > > Geert >
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index be8a0a768c65..eb57a52d2086 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -87,6 +87,59 @@ rtc: rtc@1004ec00 { status = "disabled"; }; + adc: adc@10058000 { + compatible = "renesas,r9a08g045-adc"; + reg = <0 0x10058000 0 0x400>; + interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A08G045_ADC_ADCLK>, + <&cpg CPG_MOD R9A08G045_ADC_PCLK>; + clock-names = "adclk", "pclk"; + resets = <&cpg R9A08G045_ADC_PRESETN>, + <&cpg R9A08G045_ADC_ADRST_N>; + reset-names = "presetn", "adrst-n"; + power-domains = <&cpg>; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + channel@0 { + reg = <0>; + }; + + channel@1 { + reg = <1>; + }; + + channel@2 { + reg = <2>; + }; + + channel@3 { + reg = <3>; + }; + + channel@4 { + reg = <4>; + }; + + channel@5 { + reg = <5>; + }; + + channel@6 { + reg = <6>; + }; + + channel@7 { + reg = <7>; + }; + + channel@8 { + reg = <8>; + }; + }; + vbattb: clock-controller@1005c000 { compatible = "renesas,r9a08g045-vbattb"; reg = <0 0x1005c000 0 0x1000>;