[v2,15/15] arm64: dts: renesas: rzg3s-smarc-som: Enable ADC

Message ID	20241206111337.726244-16-claudiu.beznea.uj@bp.renesas.com (mailing list archive)
State	Handled Elsewhere
Headers	show Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20B29202F91 for <linux-iio@vger.kernel.org>; Fri, 6 Dec 2024 11:14:23 +0000 (UTC) From: Claudiu <claudiu.beznea@tuxon.dev> To: prabhakar.mahadev-lad.rj@bp.renesas.com, jic23@kernel.org, lars@metafoo.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Subject: [PATCH v2 15/15] arm64: dts: renesas: rzg3s-smarc-som: Enable ADC Date: Fri, 6 Dec 2024 13:13:37 +0200 Message-Id: <20241206111337.726244-16-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20241206111337.726244-1-claudiu.beznea.uj@bp.renesas.com> References: <20241206111337.726244-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	iio: adc: rzg2l_adc: Add support for RZ/G3S \| expand [v2,00/15] iio: adc: rzg2l_adc: Add support for RZ/G3S [v2,01/15] clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP [v2,02/15] iio: adc: rzg2l_adc: Convert dev_err() to dev_err_probe() [v2,03/15] iio: adc: rzg2l_adc: Use devres helpers to request pre-deasserted reset controls [v2,04/15] iio: adc: rzg2l_adc: Simplify the runtime PM code [v2,05/15] iio: adc: rzg2l_adc: Switch to RUNTIME_PM_OPS() and pm_ptr() [v2,06/15] iio: adc: rzg2l_adc: Use read_poll_timeout() [v2,07/15] iio: adc: rzg2l_adc: Simplify the locking scheme in rzg2l_adc_read_raw() [v2,08/15] iio: adc: rzg2l_adc: Enable runtime PM autosuspend support [v2,09/15] iio: adc: rzg2l_adc: Prepare for the addition of RZ/G3S support [v2,10/15] iio: adc: rzg2l_adc: Add support for channel 8 [v2,11/15] iio: adc: rzg2l_adc: Add suspend/resume support [v2,12/15] dt-bindings: iio: adc: renesas,rzg2l-adc: Document RZ/G3S SoC [v2,13/15] iio: adc: rzg2l_adc: Add support for Renesas RZ/G3S [v2,14/15] arm64: dts: renesas: r9a08g045: Add ADC node [v2,15/15] arm64: dts: renesas: rzg3s-smarc-som: Enable ADC

Message ID

20241206111337.726244-16-claudiu.beznea.uj@bp.renesas.com (mailing list archive)

State

Handled Elsewhere

Headers

From: Claudiu <claudiu.beznea@tuxon.dev>
To: prabhakar.mahadev-lad.rj@bp.renesas.com,
	jic23@kernel.org,
	lars@metafoo.de,
	robh@kernel.org,
	krzk+dt@kernel.org,
	conor+dt@kernel.org,
	geert+renesas@glider.be,
	magnus.damm@gmail.com,
	mturquette@baylibre.com,
	sboyd@kernel.org,
	p.zabel@pengutronix.de
Cc: claudiu.beznea@tuxon.dev,
	linux-iio@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org,
	devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org,
	Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: [PATCH v2 15/15] arm64: dts: renesas: rzg3s-smarc-som: Enable ADC
Date: Fri,  6 Dec 2024 13:13:37 +0200
Message-Id: <20241206111337.726244-16-claudiu.beznea.uj@bp.renesas.com>
In-Reply-To: <20241206111337.726244-1-claudiu.beznea.uj@bp.renesas.com>
References: <20241206111337.726244-1-claudiu.beznea.uj@bp.renesas.com>
Precedence: bulk
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit

Series

iio: adc: rzg2l_adc: Add support for RZ/G3S | expand

Commit Message

Claudiu Beznea Dec. 6, 2024, 11:13 a.m. UTC

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Enable ADC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---

Changes in v2:
- none

 arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Geert Uytterhoeven Dec. 11, 2024, 1:32 p.m. UTC | #1

On Fri, Dec 6, 2024 at 12:14 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Enable ADC.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.14.

Gr{oetje,eeting}s,

                        Geert

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index 2ed01d391554..57ebdfc858eb 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -94,6 +94,10 @@  vcc_sdhi2: regulator2 {
 	};
 };
 
+&adc {
+	status = "okay";
+};
+
 #if SW_CONFIG3 == SW_ON
 &eth0 {
 	pinctrl-0 = <&eth0_pins>;

[v2,15/15] arm64: dts: renesas: rzg3s-smarc-som: Enable ADC

Commit Message

Comments

Patch