| Message ID | 20241212-imx-ocotp-v1-1-198bb0af86a0@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Make i.MX9 OCOTP work as accessing controller | expand |
On Thu, Dec 12, 2024 at 04:24:41PM +0800, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > Introduce "#access-controller-cells" to make OCOTP be an accessing > controller, because i.MX Family OCOTP supports a specific peripheral > or function being fused which means being disabled. > > Add the i.MX[95,93] OCOTP gate index. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- Nice feature! Reviewed-by: Frank Li <Frank.Li@nxp.com> > .../devicetree/bindings/nvmem/imx-ocotp.yaml | 5 +++ > include/dt-bindings/nvmem/fsl,imx93-ocotp.h | 24 ++++++++++++ > include/dt-bindings/nvmem/fsl,imx95-ocotp.h | 43 ++++++++++++++++++++++ > 3 files changed, 72 insertions(+) > > diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml b/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml > index b2cb76cf9053a883a158acaf5eaa108895818afc..c78e202ced22f1c278f7be827b71ba434832d2a7 100644 > --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml > +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml > @@ -54,6 +54,11 @@ properties: > clocks: > maxItems: 1 > > + "#access-controller-cells": > + const: 1 > + description: > + Contains the gate ID associated to the peripheral. > + > required: > - "#address-cells" > - "#size-cells" > diff --git a/include/dt-bindings/nvmem/fsl,imx93-ocotp.h b/include/dt-bindings/nvmem/fsl,imx93-ocotp.h > new file mode 100644 > index 0000000000000000000000000000000000000000..6ef525173845fd4ee0e847cf5a17e53a14f71362 > --- /dev/null > +++ b/include/dt-bindings/nvmem/fsl,imx93-ocotp.h > @@ -0,0 +1,24 @@ > +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ > + > +#ifndef _DT_BINDINGS_NVMEM_IMX93_OTPC_H > +#define _DT_BINDINGS_NVMEM_IMX93_OTPC_H > + > +#define IMX93_OCOTP_NPU_GATE 0 > +#define IMX93_OCOTP_A550_GATE 1 > +#define IMX93_OCOTP_A551_GATE 2 > +#define IMX93_OCOTP_M33_GATE 3 > +#define IMX93_OCOTP_CAN1_FD_GATE 4 > +#define IMX93_OCOTP_CAN2_FD_GATE 5 > +#define IMX93_OCOTP_CAN1_GATE 6 > +#define IMX93_OCOTP_CAN2_GATE 7 > +#define IMX93_OCOTP_USB1_GATE 8 > +#define IMX93_OCOTP_USB2_GATE 9 > +#define IMX93_OCOTP_ENET1_GATE 10 > +#define IMX93_OCOTP_ENET2_GATE 11 > +#define IMX93_OCOTP_PXP_GATE 12 > +#define IMX93_OCOTP_MIPI_CSI1_GATE 13 > +#define IMX93_OCOTP_MIPI_DSI1_GATE 14 > +#define IMX93_OCOTP_LVDS1_GATE 15 > +#define IMX93_OCOTP_ADC1_GATE 16 > + > +#endif > diff --git a/include/dt-bindings/nvmem/fsl,imx95-ocotp.h b/include/dt-bindings/nvmem/fsl,imx95-ocotp.h > new file mode 100644 > index 0000000000000000000000000000000000000000..2d21d1f690974d0215c71352168378a150f489af > --- /dev/null > +++ b/include/dt-bindings/nvmem/fsl,imx95-ocotp.h > @@ -0,0 +1,43 @@ > +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ > + > +#ifndef _DT_BINDINGS_NVMEM_IMX95_OTPC_H > +#define _DT_BINDINGS_NVMEM_IMX95_OTPC_H > + > +#define IMX95_OCOTP_CANFD1_GATE 0 > +#define IMX95_OCOTP_CANFD2_GATE 1 > +#define IMX95_OCOTP_CANFD3_GATE 2 > +#define IMX95_OCOTP_CANFD4_GATE 3 > +#define IMX95_OCOTP_CANFD5_GATE 4 > +#define IMX95_OCOTP_CAN1_GATE 5 > +#define IMX95_OCOTP_CAN2_GATE 6 > +#define IMX95_OCOTP_CAN3_GATE 7 > +#define IMX95_OCOTP_CAN4_GATE 8 > +#define IMX95_OCOTP_CAN5_GATE 9 > +#define IMX95_OCOTP_NPU_GATE 10 > +#define IMX95_OCOTP_A550_GATE 11 > +#define IMX95_OCOTP_A551_GATE 12 > +#define IMX95_OCOTP_A552_GATE 13 > +#define IMX95_OCOTP_A553_GATE 14 > +#define IMX95_OCOTP_A554_GATE 15 > +#define IMX95_OCOTP_A555_GATE 16 > +#define IMX95_OCOTP_M7_GATE 17 > +#define IMX95_OCOTP_DCSS_GATE 18 > +#define IMX95_OCOTP_LVDS1_GATE 19 > +#define IMX95_OCOTP_ISP_GATE 20 > +#define IMX95_OCOTP_USB1_GATE 21 > +#define IMX95_OCOTP_USB2_GATE 22 > +#define IMX95_OCOTP_NETC_GATE 23 > +#define IMX95_OCOTP_PCIE1_GATE 24 > +#define IMX95_OCOTP_PCIE2_GATE 25 > +#define IMX95_OCOTP_ADC1_GATE 26 > +#define IMX95_OCOTP_EARC_RX_GATE 27 > +#define IMX95_OCOTP_GPU3D_GATE 28 > +#define IMX95_OCOTP_VPU_GATE 29 > +#define IMX95_OCOTP_JPEG_ENC_GATE 30 > +#define IMX95_OCOTP_JPEG_DEC_GATE 31 > +#define IMX95_OCOTP_MIPI_CSI1_GATE 32 > +#define IMX95_OCOTP_MIPI_CSI2_GATE 33 > +#define IMX95_OCOTP_MIPI_DSI1_GATE 34 > +#define IMX95_OCOTP_V2X_GATE 35 > + > +#endif > > -- > 2.37.1 >
diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml b/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml index b2cb76cf9053a883a158acaf5eaa108895818afc..c78e202ced22f1c278f7be827b71ba434832d2a7 100644 --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml @@ -54,6 +54,11 @@ properties: clocks: maxItems: 1 + "#access-controller-cells": + const: 1 + description: + Contains the gate ID associated to the peripheral. + required: - "#address-cells" - "#size-cells" diff --git a/include/dt-bindings/nvmem/fsl,imx93-ocotp.h b/include/dt-bindings/nvmem/fsl,imx93-ocotp.h new file mode 100644 index 0000000000000000000000000000000000000000..6ef525173845fd4ee0e847cf5a17e53a14f71362 --- /dev/null +++ b/include/dt-bindings/nvmem/fsl,imx93-ocotp.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ + +#ifndef _DT_BINDINGS_NVMEM_IMX93_OTPC_H +#define _DT_BINDINGS_NVMEM_IMX93_OTPC_H + +#define IMX93_OCOTP_NPU_GATE 0 +#define IMX93_OCOTP_A550_GATE 1 +#define IMX93_OCOTP_A551_GATE 2 +#define IMX93_OCOTP_M33_GATE 3 +#define IMX93_OCOTP_CAN1_FD_GATE 4 +#define IMX93_OCOTP_CAN2_FD_GATE 5 +#define IMX93_OCOTP_CAN1_GATE 6 +#define IMX93_OCOTP_CAN2_GATE 7 +#define IMX93_OCOTP_USB1_GATE 8 +#define IMX93_OCOTP_USB2_GATE 9 +#define IMX93_OCOTP_ENET1_GATE 10 +#define IMX93_OCOTP_ENET2_GATE 11 +#define IMX93_OCOTP_PXP_GATE 12 +#define IMX93_OCOTP_MIPI_CSI1_GATE 13 +#define IMX93_OCOTP_MIPI_DSI1_GATE 14 +#define IMX93_OCOTP_LVDS1_GATE 15 +#define IMX93_OCOTP_ADC1_GATE 16 + +#endif diff --git a/include/dt-bindings/nvmem/fsl,imx95-ocotp.h b/include/dt-bindings/nvmem/fsl,imx95-ocotp.h new file mode 100644 index 0000000000000000000000000000000000000000..2d21d1f690974d0215c71352168378a150f489af --- /dev/null +++ b/include/dt-bindings/nvmem/fsl,imx95-ocotp.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ + +#ifndef _DT_BINDINGS_NVMEM_IMX95_OTPC_H +#define _DT_BINDINGS_NVMEM_IMX95_OTPC_H + +#define IMX95_OCOTP_CANFD1_GATE 0 +#define IMX95_OCOTP_CANFD2_GATE 1 +#define IMX95_OCOTP_CANFD3_GATE 2 +#define IMX95_OCOTP_CANFD4_GATE 3 +#define IMX95_OCOTP_CANFD5_GATE 4 +#define IMX95_OCOTP_CAN1_GATE 5 +#define IMX95_OCOTP_CAN2_GATE 6 +#define IMX95_OCOTP_CAN3_GATE 7 +#define IMX95_OCOTP_CAN4_GATE 8 +#define IMX95_OCOTP_CAN5_GATE 9 +#define IMX95_OCOTP_NPU_GATE 10 +#define IMX95_OCOTP_A550_GATE 11 +#define IMX95_OCOTP_A551_GATE 12 +#define IMX95_OCOTP_A552_GATE 13 +#define IMX95_OCOTP_A553_GATE 14 +#define IMX95_OCOTP_A554_GATE 15 +#define IMX95_OCOTP_A555_GATE 16 +#define IMX95_OCOTP_M7_GATE 17 +#define IMX95_OCOTP_DCSS_GATE 18 +#define IMX95_OCOTP_LVDS1_GATE 19 +#define IMX95_OCOTP_ISP_GATE 20 +#define IMX95_OCOTP_USB1_GATE 21 +#define IMX95_OCOTP_USB2_GATE 22 +#define IMX95_OCOTP_NETC_GATE 23 +#define IMX95_OCOTP_PCIE1_GATE 24 +#define IMX95_OCOTP_PCIE2_GATE 25 +#define IMX95_OCOTP_ADC1_GATE 26 +#define IMX95_OCOTP_EARC_RX_GATE 27 +#define IMX95_OCOTP_GPU3D_GATE 28 +#define IMX95_OCOTP_VPU_GATE 29 +#define IMX95_OCOTP_JPEG_ENC_GATE 30 +#define IMX95_OCOTP_JPEG_DEC_GATE 31 +#define IMX95_OCOTP_MIPI_CSI1_GATE 32 +#define IMX95_OCOTP_MIPI_CSI2_GATE 33 +#define IMX95_OCOTP_MIPI_DSI1_GATE 34 +#define IMX95_OCOTP_V2X_GATE 35 + +#endif