| Message ID | 20241216031225.3746-12-damon.ding@rock-chips.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add eDP support for RK3588 | expand |
Hi Damon, Am Montag, 16. Dezember 2024, 04:12:25 CET schrieb Damon Ding: > The related nodes are hdptxphy1_grf, hdptxphy1 and edp1. And the > aliases edp0 and edp1 are added to separate two independent eDP > devices. > > Signed-off-by: Damon Ding <damon.ding@rock-chips.com> > --- > .../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 55 +++++++++++++++++++ > 1 file changed, 55 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi > index 0ce0934ec6b7..17cc0b619744 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi > @@ -7,6 +7,11 @@ > #include "rk3588-extra-pinctrl.dtsi" > > / { > + aliases { > + edp0 = &edp0; > + edp1 = &edp1; > + }; > + drop aliases please > @@ -67,6 +72,11 @@ u2phy1_otg: otg-port { > }; > }; > > + hdptxphy1_grf: syscon@fd5e4000 { > + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; > + reg = <0x0 0xfd5e4000 0x0 0x100>; > + }; > + > i2s8_8ch: i2s@fddc8000 { > compatible = "rockchip,rk3588-i2s-tdm"; > reg = <0x0 0xfddc8000 0x0 0x1000>; > @@ -395,6 +434,22 @@ sata-port@0 { > }; > }; > > + hdptxphy1: phy@fed70000 { > + compatible = "rockchip,rk3588-hdptx-phy"; > + reg = <0x0 0xfed70000 0x0 0x2000>; > + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; > + clock-names = "ref", "apb"; > + #phy-cells = <0>; > + resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, > + <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, > + <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, > + <&cru SRST_HDPTX1_LCPLL>; > + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", > + "lcpll"; > + rockchip,grf = <&hdptxphy1_grf>; > + status = "disabled"; > + }; the hdptxphy nodes should be their own patch, also because most likely Cristian's patch for hdmi1 [0] will be slightly faster. [0] https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-2-02cdca22ff68@collabora.com
Hi Heiko, On 2024/12/18 20:45, Heiko Stübner wrote: > Hi Damon, > > Am Montag, 16. Dezember 2024, 04:12:25 CET schrieb Damon Ding: >> The related nodes are hdptxphy1_grf, hdptxphy1 and edp1. And the >> aliases edp0 and edp1 are added to separate two independent eDP >> devices. >> >> Signed-off-by: Damon Ding <damon.ding@rock-chips.com> >> --- >> .../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 55 +++++++++++++++++++ >> 1 file changed, 55 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi >> index 0ce0934ec6b7..17cc0b619744 100644 >> --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi >> +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi >> @@ -7,6 +7,11 @@ >> #include "rk3588-extra-pinctrl.dtsi" >> >> / { >> + aliases { >> + edp0 = &edp0; >> + edp1 = &edp1; >> + }; >> + > > drop aliases please I will drop it and use the registers to separate edp0 and edp1 in the next version. > > >> @@ -67,6 +72,11 @@ u2phy1_otg: otg-port { >> }; >> }; >> >> + hdptxphy1_grf: syscon@fd5e4000 { >> + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; >> + reg = <0x0 0xfd5e4000 0x0 0x100>; >> + }; >> + >> i2s8_8ch: i2s@fddc8000 { >> compatible = "rockchip,rk3588-i2s-tdm"; >> reg = <0x0 0xfddc8000 0x0 0x1000>; > >> @@ -395,6 +434,22 @@ sata-port@0 { >> }; >> }; >> >> + hdptxphy1: phy@fed70000 { >> + compatible = "rockchip,rk3588-hdptx-phy"; >> + reg = <0x0 0xfed70000 0x0 0x2000>; >> + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; >> + clock-names = "ref", "apb"; >> + #phy-cells = <0>; >> + resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, >> + <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, >> + <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, >> + <&cru SRST_HDPTX1_LCPLL>; >> + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", >> + "lcpll"; >> + rockchip,grf = <&hdptxphy1_grf>; >> + status = "disabled"; >> + }; > > the hdptxphy nodes should be their own patch, also because most likely > Cristian's patch for hdmi1 [0] will be slightly faster. Indeed, it is good to add edp1 node only. > > > [0] https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-2-02cdca22ff68@collabora.com > > > > > Best regards, Damon
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index 0ce0934ec6b7..17cc0b619744 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -7,6 +7,11 @@ #include "rk3588-extra-pinctrl.dtsi" / { + aliases { + edp0 = &edp0; + edp1 = &edp1; + }; + usb_host1_xhci: usb@fc400000 { compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; reg = <0x0 0xfc400000 0x0 0x400000>; @@ -67,6 +72,11 @@ u2phy1_otg: otg-port { }; }; + hdptxphy1_grf: syscon@fd5e4000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e4000 0x0 0x100>; + }; + i2s8_8ch: i2s@fddc8000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc8000 0x0 0x1000>; @@ -135,6 +145,35 @@ i2s10_8ch: i2s@fde00000 { status = "disabled"; }; + edp1: edp@fded0000 { + compatible = "rockchip,rk3588-edp"; + reg = <0x0 0xfded0000 0x0 0x1000>; + clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>, <&cru CLK_EDP1_200M>; + clock-names = "dp", "pclk", "spdif"; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; + phys = <&hdptxphy1>; + phy-names = "dp"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_EDP1_24M>, <&cru SRST_P_EDP1>; + reset-names = "dp", "apb"; + rockchip,grf = <&vo1_grf>; + #sound-dai-cells = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + edp1_in: port@0 { + reg = <0>; + }; + + edp1_out: port@1 { + reg = <1>; + }; + }; + }; + pcie3x4: pcie@fe150000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; #address-cells = <3>; @@ -395,6 +434,22 @@ sata-port@0 { }; }; + hdptxphy1: phy@fed70000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed70000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; + clock-names = "ref", "apb"; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, + <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, + <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, + <&cru SRST_HDPTX1_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy1_grf>; + status = "disabled"; + }; + usbdp_phy1: phy@fed90000 { compatible = "rockchip,rk3588-usbdp-phy"; reg = <0x0 0xfed90000 0x0 0x10000>;
The related nodes are hdptxphy1_grf, hdptxphy1 and edp1. And the aliases edp0 and edp1 are added to separate two independent eDP devices. Signed-off-by: Damon Ding <damon.ding@rock-chips.com> --- .../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+)