| Message ID | 20241219131029.1139720-2-ciprianmarian.costea@oss.nxp.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | add I2C DTS support for S32G2/S32G3 SoCs | expand |
On Thu, Dec 19, 2024 at 03:10:26PM +0200, Ciprian Costea wrote: > From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> > > On both 'S32G2' and 'S32G3' SoCs there are five i2c controllers available > (i2c0-i2c4). Specific S32G2/S32G3 based board 'i2c' dts device support > will be added in further commits. > > Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> > --- > arch/arm64/boot/dts/freescale/s32g2.dtsi | 45 +++++++++++++++++++++ > arch/arm64/boot/dts/freescale/s32g3.dtsi | 50 ++++++++++++++++++++++++ > 2 files changed, 95 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi > index 7be430b78c83..0e6c847ab0c3 100644 > --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi > @@ -333,6 +333,33 @@ uart1: serial@401cc000 { > status = "disabled"; > }; > > + i2c0: i2c@401e4000 { > + compatible = "nxp,s32g2-i2c"; > + reg = <0x401e4000 0x1000>; Need add common part #address-cell and #size-cell, which all are the same for all I2C. Frank > + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks 40>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + i2c1: i2c@401e8000 { > + compatible = "nxp,s32g2-i2c"; > + reg = <0x401e8000 0x1000>; > + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks 40>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + i2c2: i2c@401ec000 { > + compatible = "nxp,s32g2-i2c"; > + reg = <0x401ec000 0x1000>; > + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks 40>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > uart2: serial@402bc000 { > compatible = "nxp,s32g2-linflexuart", > "fsl,s32v234-linflexuart"; > @@ -341,6 +368,24 @@ uart2: serial@402bc000 { > status = "disabled"; > }; > > + i2c3: i2c@402d8000 { > + compatible = "nxp,s32g2-i2c"; > + reg = <0x402d8000 0x1000>; > + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks 40>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + i2c4: i2c@402dc000 { > + compatible = "nxp,s32g2-i2c"; > + reg = <0x402dc000 0x1000>; > + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks 40>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > usdhc0: mmc@402f0000 { > compatible = "nxp,s32g2-usdhc"; > reg = <0x402f0000 0x1000>; > diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi > index 6c572ffe37ca..666e4029e588 100644 > --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi > @@ -390,6 +390,36 @@ uart1: serial@401cc000 { > status = "disabled"; > }; > > + i2c0: i2c@401e4000 { > + compatible = "nxp,s32g3-i2c", > + "nxp,s32g2-i2c"; > + reg = <0x401e4000 0x1000>; > + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks 40>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + i2c1: i2c@401e8000 { > + compatible = "nxp,s32g3-i2c", > + "nxp,s32g2-i2c"; > + reg = <0x401e8000 0x1000>; > + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks 40>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + i2c2: i2c@401ec000 { > + compatible = "nxp,s32g3-i2c", > + "nxp,s32g2-i2c"; > + reg = <0x401ec000 0x1000>; > + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks 40>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > uart2: serial@402bc000 { > compatible = "nxp,s32g3-linflexuart", > "fsl,s32v234-linflexuart"; > @@ -398,6 +428,26 @@ uart2: serial@402bc000 { > status = "disabled"; > }; > > + i2c3: i2c@402d8000 { > + compatible = "nxp,s32g3-i2c", > + "nxp,s32g2-i2c"; > + reg = <0x402d8000 0x1000>; > + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks 40>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + i2c4: i2c@402dc000 { > + compatible = "nxp,s32g3-i2c", > + "nxp,s32g2-i2c"; > + reg = <0x402dc000 0x1000>; > + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks 40>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > usdhc0: mmc@402f0000 { > compatible = "nxp,s32g3-usdhc", > "nxp,s32g2-usdhc"; > -- > 2.45.2 >
On 12/19/2024 7:17 PM, Frank Li wrote: > On Thu, Dec 19, 2024 at 03:10:26PM +0200, Ciprian Costea wrote: >> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> >> >> On both 'S32G2' and 'S32G3' SoCs there are five i2c controllers available >> (i2c0-i2c4). Specific S32G2/S32G3 based board 'i2c' dts device support >> will be added in further commits. >> >> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> >> --- >> arch/arm64/boot/dts/freescale/s32g2.dtsi | 45 +++++++++++++++++++++ >> arch/arm64/boot/dts/freescale/s32g3.dtsi | 50 ++++++++++++++++++++++++ >> 2 files changed, 95 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi >> index 7be430b78c83..0e6c847ab0c3 100644 >> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi >> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi >> @@ -333,6 +333,33 @@ uart1: serial@401cc000 { >> status = "disabled"; >> }; >> >> + i2c0: i2c@401e4000 { >> + compatible = "nxp,s32g2-i2c"; >> + reg = <0x401e4000 0x1000>; > > Need add common part #address-cell and #size-cell, which all are the same > for all I2C. > > Frank > Hello Frank, Ok, I will update accordingly in V4. Best Regards, Ciprian >> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&clks 40>; >> + clock-names = "ipg"; >> + status = "disabled"; >> + }; >> + >> + i2c1: i2c@401e8000 { >> + compatible = "nxp,s32g2-i2c"; >> + reg = <0x401e8000 0x1000>; >> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&clks 40>; >> + clock-names = "ipg"; >> + status = "disabled"; >> + }; >> + >> + i2c2: i2c@401ec000 { >> + compatible = "nxp,s32g2-i2c"; >> + reg = <0x401ec000 0x1000>; >> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&clks 40>; >> + clock-names = "ipg"; >> + status = "disabled"; >> + }; >> + >> uart2: serial@402bc000 { >> compatible = "nxp,s32g2-linflexuart", >> "fsl,s32v234-linflexuart"; >> @@ -341,6 +368,24 @@ uart2: serial@402bc000 { >> status = "disabled"; >> }; >> >> + i2c3: i2c@402d8000 { >> + compatible = "nxp,s32g2-i2c"; >> + reg = <0x402d8000 0x1000>; >> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&clks 40>; >> + clock-names = "ipg"; >> + status = "disabled"; >> + }; >> + >> + i2c4: i2c@402dc000 { >> + compatible = "nxp,s32g2-i2c"; >> + reg = <0x402dc000 0x1000>; >> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&clks 40>; >> + clock-names = "ipg"; >> + status = "disabled"; >> + }; >> + >> usdhc0: mmc@402f0000 { >> compatible = "nxp,s32g2-usdhc"; >> reg = <0x402f0000 0x1000>; >> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi >> index 6c572ffe37ca..666e4029e588 100644 >> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi >> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi >> @@ -390,6 +390,36 @@ uart1: serial@401cc000 { >> status = "disabled"; >> }; >> >> + i2c0: i2c@401e4000 { >> + compatible = "nxp,s32g3-i2c", >> + "nxp,s32g2-i2c"; >> + reg = <0x401e4000 0x1000>; >> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&clks 40>; >> + clock-names = "ipg"; >> + status = "disabled"; >> + }; >> + >> + i2c1: i2c@401e8000 { >> + compatible = "nxp,s32g3-i2c", >> + "nxp,s32g2-i2c"; >> + reg = <0x401e8000 0x1000>; >> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&clks 40>; >> + clock-names = "ipg"; >> + status = "disabled"; >> + }; >> + >> + i2c2: i2c@401ec000 { >> + compatible = "nxp,s32g3-i2c", >> + "nxp,s32g2-i2c"; >> + reg = <0x401ec000 0x1000>; >> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&clks 40>; >> + clock-names = "ipg"; >> + status = "disabled"; >> + }; >> + >> uart2: serial@402bc000 { >> compatible = "nxp,s32g3-linflexuart", >> "fsl,s32v234-linflexuart"; >> @@ -398,6 +428,26 @@ uart2: serial@402bc000 { >> status = "disabled"; >> }; >> >> + i2c3: i2c@402d8000 { >> + compatible = "nxp,s32g3-i2c", >> + "nxp,s32g2-i2c"; >> + reg = <0x402d8000 0x1000>; >> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&clks 40>; >> + clock-names = "ipg"; >> + status = "disabled"; >> + }; >> + >> + i2c4: i2c@402dc000 { >> + compatible = "nxp,s32g3-i2c", >> + "nxp,s32g2-i2c"; >> + reg = <0x402dc000 0x1000>; >> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&clks 40>; >> + clock-names = "ipg"; >> + status = "disabled"; >> + }; >> + >> usdhc0: mmc@402f0000 { >> compatible = "nxp,s32g3-usdhc", >> "nxp,s32g2-usdhc"; >> -- >> 2.45.2 >>
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 7be430b78c83..0e6c847ab0c3 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -333,6 +333,33 @@ uart1: serial@401cc000 { status = "disabled"; }; + i2c0: i2c@401e4000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401e4000 0x1000>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c1: i2c@401e8000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401e8000 0x1000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c2: i2c@401ec000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401ec000 0x1000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + uart2: serial@402bc000 { compatible = "nxp,s32g2-linflexuart", "fsl,s32v234-linflexuart"; @@ -341,6 +368,24 @@ uart2: serial@402bc000 { status = "disabled"; }; + i2c3: i2c@402d8000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x402d8000 0x1000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c4: i2c@402dc000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x402dc000 0x1000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + usdhc0: mmc@402f0000 { compatible = "nxp,s32g2-usdhc"; reg = <0x402f0000 0x1000>; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 6c572ffe37ca..666e4029e588 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -390,6 +390,36 @@ uart1: serial@401cc000 { status = "disabled"; }; + i2c0: i2c@401e4000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x401e4000 0x1000>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c1: i2c@401e8000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x401e8000 0x1000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c2: i2c@401ec000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x401ec000 0x1000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + uart2: serial@402bc000 { compatible = "nxp,s32g3-linflexuart", "fsl,s32v234-linflexuart"; @@ -398,6 +428,26 @@ uart2: serial@402bc000 { status = "disabled"; }; + i2c3: i2c@402d8000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x402d8000 0x1000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c4: i2c@402dc000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x402dc000 0x1000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + usdhc0: mmc@402f0000 { compatible = "nxp,s32g3-usdhc", "nxp,s32g2-usdhc";