| Message ID | 20241219-correct_gpio_ranges-v2-6-19af8588dbd0@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300 | expand |
On 19.12.2024 8:59 AM, Lijuan Gao wrote: > Correct the gpio-ranges for the QCS8300 TLMM pin controller to include > GPIOs 0-132 and the UFS_RESET pin for primary UFS memory reset. > > Fixes: 7be190e4bdd2 ("arm64: dts: qcom: add QCS8300 platform") > Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Konrad
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 73abf2ef9c9f..07d6d3ff4365 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -971,7 +971,7 @@ tlmm: pinctrl@f100000 { interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 133>; + gpio-ranges = <&tlmm 0 0 134>; interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>;
Correct the gpio-ranges for the QCS8300 TLMM pin controller to include GPIOs 0-132 and the UFS_RESET pin for primary UFS memory reset. Fixes: 7be190e4bdd2 ("arm64: dts: qcom: add QCS8300 platform") Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)