| Message ID | 20241219210019.70532-1-rodrigo.vivi@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915/dg1: Fix power gate sequence. | expand |
On 12/19/2024 1:00 PM, Rodrigo Vivi wrote: > sub-pipe PG is not present on DG1. Setting these bits can disable > other power gates and cause GPU hangs on video playbacks. LGTM, Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > > VLK: 16314, 4304 > > Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13381 > Fixes: 85a12d7eb8fe ("drm/i915/tgl: Fix Media power gate sequence.") > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c > index c864d101faf9..9378d5901c49 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c > @@ -133,7 +133,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) > GEN9_MEDIA_PG_ENABLE | > GEN11_MEDIA_SAMPLER_PG_ENABLE; > > - if (GRAPHICS_VER(gt->i915) >= 12) { > + if (GRAPHICS_VER(gt->i915) >= 12 && !IS_DG1(gt->i915)) { > for (i = 0; i < I915_MAX_VCS; i++) > if (HAS_ENGINE(gt, _VCS(i))) > pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
On 20-12-2024 02:30, Rodrigo Vivi wrote: > sub-pipe PG is not present on DG1. Setting these bits can disable > other power gates and cause GPU hangs on video playbacks. > > VLK: 16314, 4304 > > Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13381 > Fixes: 85a12d7eb8fe ("drm/i915/tgl: Fix Media power gate sequence.") > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c > index c864d101faf9..9378d5901c49 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c > @@ -133,7 +133,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) > GEN9_MEDIA_PG_ENABLE | > GEN11_MEDIA_SAMPLER_PG_ENABLE; > > - if (GRAPHICS_VER(gt->i915) >= 12) { > + if (GRAPHICS_VER(gt->i915) >= 12 && !IS_DG1(gt->i915)) { Looks good to me. Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> > for (i = 0; i < I915_MAX_VCS; i++) > if (HAS_ENGINE(gt, _VCS(i))) > pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index c864d101faf9..9378d5901c49 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -133,7 +133,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) GEN9_MEDIA_PG_ENABLE | GEN11_MEDIA_SAMPLER_PG_ENABLE; - if (GRAPHICS_VER(gt->i915) >= 12) { + if (GRAPHICS_VER(gt->i915) >= 12 && !IS_DG1(gt->i915)) { for (i = 0; i < I915_MAX_VCS; i++) if (HAS_ENGINE(gt, _VCS(i))) pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
sub-pipe PG is not present on DG1. Setting these bits can disable other power gates and cause GPU hangs on video playbacks. VLK: 16314, 4304 Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13381 Fixes: 85a12d7eb8fe ("drm/i915/tgl: Fix Media power gate sequence.") Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)