| Message ID | 20241216175414.1953-3-alireza.sanaee@huawei.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Specifying cache topology on ARM | expand |
On Mon, 16 Dec 2024 17:54:09 +0000 Alireza Sanaee <alireza.sanaee@huawei.com> wrote: > This patch addresses cache description in the `aarch64_max_tcg_initfn` > function for cpu=max. It introduces three layers of caches and modifies > the cache description registers accordingly. > > Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> I think this makes sense as a MAX cpu with out an L3 sounds pretty minimal and it provides a way to exercise the rest of this series in TCG. For KVM it will come from host registers (or overridden ones) anyway. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > target/arm/tcg/cpu64.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c > index 904a7e90b4..47d8c9c9ae 100644 > --- a/target/arm/tcg/cpu64.c > +++ b/target/arm/tcg/cpu64.c > @@ -1086,6 +1086,19 @@ void aarch64_max_tcg_initfn(Object *obj) > uint64_t t; > uint32_t u; > > + /* > + * Expanded cache set > + */ > + cpu->clidr = 0x8200123; /* 4 4 3 in 3 bit fields */ > + /* 64KB L1 dcache */ > + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); > + /* 64KB L1 icache */ > + cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); > + /* 1MB L2 unified cache */ > + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7); > + /* 2MB L3 unified cache */ > + cpu->ccsidr[4] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 * MiB, 7); > + > /* > * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default > * to because we started with aarch64_a57_initfn(). A 'max' CPU might
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 904a7e90b4..47d8c9c9ae 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1086,6 +1086,19 @@ void aarch64_max_tcg_initfn(Object *obj) uint64_t t; uint32_t u; + /* + * Expanded cache set + */ + cpu->clidr = 0x8200123; /* 4 4 3 in 3 bit fields */ + /* 64KB L1 dcache */ + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); + /* 64KB L1 icache */ + cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); + /* 1MB L2 unified cache */ + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7); + /* 2MB L3 unified cache */ + cpu->ccsidr[4] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 * MiB, 7); + /* * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default * to because we started with aarch64_a57_initfn(). A 'max' CPU might
This patch addresses cache description in the `aarch64_max_tcg_initfn` function for cpu=max. It introduces three layers of caches and modifies the cache description registers accordingly. Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> --- target/arm/tcg/cpu64.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)