| Message ID | 20241219112733.47907-1-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/mediatek: mtk_dsi: Add registers to pdata to fix MT8186/MT8188 | expand |
Hi, Angelo: On Thu, 2024-12-19 at 12:27 +0100, AngeloGioacchino Del Regno wrote: > External email : Please do not click links or open attachments until you have verified the sender or the content. > > > Registers DSI_VM_CMD and DSI_SHADOW_DEBUG start at different > addresses in both MT8186 and MT8188 compared to the older IPs. > > Add two members in struct mtk_dsi_driver_data to specify the > offsets for these two registers on a per-SoC basis, then do > specify those in all of the currently present SoC driver data. > > This fixes writes to the Video Mode Command Packet Control > register, fixing enablement of command packet transmission > (VM_CMD_EN) and allowance of this transmission during the > VFP period (TS_VFP_EN) on both MT8186 and MT8188. Reviewed-by: CK Hu <ck.hu@mediatek.com> I'm curious that only some panel has problem without this patch? I think the fixed-patch sender has test on their panel. Regards, CK > > Fixes: 03d7adc41027 ("drm/mediatek: Add mt8186 dsi compatible to mtk_dsi.c") > Fixes: 814d5341f314 ("drm/mediatek: Add mt8188 dsi compatible to mtk_dsi.c") > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 22 +++++++++++++++++----- > 1 file changed, 17 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c > index e61b9bc68e9a..978332cd52f5 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -139,11 +139,11 @@ > #define CLK_HS_POST GENMASK(15, 8) > #define CLK_HS_EXIT GENMASK(23, 16) > > -#define DSI_VM_CMD_CON 0x130 > +/* DSI_VM_CMD_CON */ > #define VM_CMD_EN BIT(0) > #define TS_VFP_EN BIT(5) > > -#define DSI_SHADOW_DEBUG 0x190U > +/* DSI_SHADOW_DEBUG */ > #define FORCE_COMMIT BIT(0) > #define BYPASS_SHADOW BIT(1) > > @@ -187,6 +187,8 @@ struct phy; > > struct mtk_dsi_driver_data { > const u32 reg_cmdq_off; > + const u32 reg_vm_cmd_off; > + const u32 reg_shadow_dbg_off; > bool has_shadow_ctl; > bool has_size_ctl; > bool cmdq_long_packet_ctl; > @@ -367,8 +369,8 @@ static void mtk_dsi_set_mode(struct mtk_dsi *dsi) > > static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) > { > - mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN); > - mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); > + mtk_dsi_mask(dsi, dsi->driver_data->reg_vm_cmd_off, VM_CMD_EN, VM_CMD_EN); > + mtk_dsi_mask(dsi, dsi->driver_data->reg_vm_cmd_off, TS_VFP_EN, TS_VFP_EN); > } > > static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) > @@ -714,7 +716,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > > if (dsi->driver_data->has_shadow_ctl) > writel(FORCE_COMMIT | BYPASS_SHADOW, > - dsi->regs + DSI_SHADOW_DEBUG); > + dsi->regs + dsi->driver_data->reg_shadow_dbg_off); > > mtk_dsi_reset_engine(dsi); > mtk_dsi_phy_timconfig(dsi); > @@ -1263,26 +1265,36 @@ static void mtk_dsi_remove(struct platform_device *pdev) > > static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = { > .reg_cmdq_off = 0x200, > + .reg_vm_cmd_off = 0x130, > + .reg_shadow_dbg_off = 0x190 > }; > > static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = { > .reg_cmdq_off = 0x180, > + .reg_vm_cmd_off = 0x130, > + .reg_shadow_dbg_off = 0x190 > }; > > static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = { > .reg_cmdq_off = 0x200, > + .reg_vm_cmd_off = 0x130, > + .reg_shadow_dbg_off = 0x190, > .has_shadow_ctl = true, > .has_size_ctl = true, > }; > > static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = { > .reg_cmdq_off = 0xd00, > + .reg_vm_cmd_off = 0x200, > + .reg_shadow_dbg_off = 0xc00, > .has_shadow_ctl = true, > .has_size_ctl = true, > }; > > static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = { > .reg_cmdq_off = 0xd00, > + .reg_vm_cmd_off = 0x200, > + .reg_shadow_dbg_off = 0xc00, > .has_shadow_ctl = true, > .has_size_ctl = true, > .cmdq_long_packet_ctl = true, > -- > 2.47.0 >
Il 24/12/24 06:36, CK Hu (胡俊光) ha scritto: > Hi, Angelo: > > On Thu, 2024-12-19 at 12:27 +0100, AngeloGioacchino Del Regno wrote: >> External email : Please do not click links or open attachments until you have verified the sender or the content. >> >> >> Registers DSI_VM_CMD and DSI_SHADOW_DEBUG start at different >> addresses in both MT8186 and MT8188 compared to the older IPs. >> >> Add two members in struct mtk_dsi_driver_data to specify the >> offsets for these two registers on a per-SoC basis, then do >> specify those in all of the currently present SoC driver data. >> >> This fixes writes to the Video Mode Command Packet Control >> register, fixing enablement of command packet transmission >> (VM_CMD_EN) and allowance of this transmission during the >> VFP period (TS_VFP_EN) on both MT8186 and MT8188. > > Reviewed-by: CK Hu <ck.hu@mediatek.com> > > I'm curious that only some panel has problem without this patch? > I think the fixed-patch sender has test on their panel. > I think that depends on how the bootloader leaves the DSI registers before booting Linux... but anyway, this was tested on the Startek panel found on the latest HW revision of the Genio 700 EVK :-) Cheers, Angelo > Regards, > CK > >> >> Fixes: 03d7adc41027 ("drm/mediatek: Add mt8186 dsi compatible to mtk_dsi.c") >> Fixes: 814d5341f314 ("drm/mediatek: Add mt8188 dsi compatible to mtk_dsi.c") >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >> --- >> drivers/gpu/drm/mediatek/mtk_dsi.c | 22 +++++++++++++++++----- >> 1 file changed, 17 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c >> index e61b9bc68e9a..978332cd52f5 100644 >> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c >> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c >> @@ -139,11 +139,11 @@ >> #define CLK_HS_POST GENMASK(15, 8) >> #define CLK_HS_EXIT GENMASK(23, 16) >> >> -#define DSI_VM_CMD_CON 0x130 >> +/* DSI_VM_CMD_CON */ >> #define VM_CMD_EN BIT(0) >> #define TS_VFP_EN BIT(5) >> >> -#define DSI_SHADOW_DEBUG 0x190U >> +/* DSI_SHADOW_DEBUG */ >> #define FORCE_COMMIT BIT(0) >> #define BYPASS_SHADOW BIT(1) >> >> @@ -187,6 +187,8 @@ struct phy; >> >> struct mtk_dsi_driver_data { >> const u32 reg_cmdq_off; >> + const u32 reg_vm_cmd_off; >> + const u32 reg_shadow_dbg_off; >> bool has_shadow_ctl; >> bool has_size_ctl; >> bool cmdq_long_packet_ctl; >> @@ -367,8 +369,8 @@ static void mtk_dsi_set_mode(struct mtk_dsi *dsi) >> >> static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) >> { >> - mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN); >> - mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); >> + mtk_dsi_mask(dsi, dsi->driver_data->reg_vm_cmd_off, VM_CMD_EN, VM_CMD_EN); >> + mtk_dsi_mask(dsi, dsi->driver_data->reg_vm_cmd_off, TS_VFP_EN, TS_VFP_EN); >> } >> >> static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) >> @@ -714,7 +716,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) >> >> if (dsi->driver_data->has_shadow_ctl) >> writel(FORCE_COMMIT | BYPASS_SHADOW, >> - dsi->regs + DSI_SHADOW_DEBUG); >> + dsi->regs + dsi->driver_data->reg_shadow_dbg_off); >> >> mtk_dsi_reset_engine(dsi); >> mtk_dsi_phy_timconfig(dsi); >> @@ -1263,26 +1265,36 @@ static void mtk_dsi_remove(struct platform_device *pdev) >> >> static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = { >> .reg_cmdq_off = 0x200, >> + .reg_vm_cmd_off = 0x130, >> + .reg_shadow_dbg_off = 0x190 >> }; >> >> static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = { >> .reg_cmdq_off = 0x180, >> + .reg_vm_cmd_off = 0x130, >> + .reg_shadow_dbg_off = 0x190 >> }; >> >> static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = { >> .reg_cmdq_off = 0x200, >> + .reg_vm_cmd_off = 0x130, >> + .reg_shadow_dbg_off = 0x190, >> .has_shadow_ctl = true, >> .has_size_ctl = true, >> }; >> >> static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = { >> .reg_cmdq_off = 0xd00, >> + .reg_vm_cmd_off = 0x200, >> + .reg_shadow_dbg_off = 0xc00, >> .has_shadow_ctl = true, >> .has_size_ctl = true, >> }; >> >> static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = { >> .reg_cmdq_off = 0xd00, >> + .reg_vm_cmd_off = 0x200, >> + .reg_shadow_dbg_off = 0xc00, >> .has_shadow_ctl = true, >> .has_size_ctl = true, >> .cmdq_long_packet_ctl = true, >> -- >> 2.47.0 >> >
Hi, Angelo: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 於 2024年12月19日 週四 下午7:27寫道： > > Registers DSI_VM_CMD and DSI_SHADOW_DEBUG start at different > addresses in both MT8186 and MT8188 compared to the older IPs. > > Add two members in struct mtk_dsi_driver_data to specify the > offsets for these two registers on a per-SoC basis, then do > specify those in all of the currently present SoC driver data. > > This fixes writes to the Video Mode Command Packet Control > register, fixing enablement of command packet transmission > (VM_CMD_EN) and allowance of this transmission during the > VFP period (TS_VFP_EN) on both MT8186 and MT8188. Applied to mediatek-drm-fixes [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-fixes Regards, Chun-Kuang. > > Fixes: 03d7adc41027 ("drm/mediatek: Add mt8186 dsi compatible to mtk_dsi.c") > Fixes: 814d5341f314 ("drm/mediatek: Add mt8188 dsi compatible to mtk_dsi.c") > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 22 +++++++++++++++++----- > 1 file changed, 17 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c > index e61b9bc68e9a..978332cd52f5 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -139,11 +139,11 @@ > #define CLK_HS_POST GENMASK(15, 8) > #define CLK_HS_EXIT GENMASK(23, 16) > > -#define DSI_VM_CMD_CON 0x130 > +/* DSI_VM_CMD_CON */ > #define VM_CMD_EN BIT(0) > #define TS_VFP_EN BIT(5) > > -#define DSI_SHADOW_DEBUG 0x190U > +/* DSI_SHADOW_DEBUG */ > #define FORCE_COMMIT BIT(0) > #define BYPASS_SHADOW BIT(1) > > @@ -187,6 +187,8 @@ struct phy; > > struct mtk_dsi_driver_data { > const u32 reg_cmdq_off; > + const u32 reg_vm_cmd_off; > + const u32 reg_shadow_dbg_off; > bool has_shadow_ctl; > bool has_size_ctl; > bool cmdq_long_packet_ctl; > @@ -367,8 +369,8 @@ static void mtk_dsi_set_mode(struct mtk_dsi *dsi) > > static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) > { > - mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN); > - mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); > + mtk_dsi_mask(dsi, dsi->driver_data->reg_vm_cmd_off, VM_CMD_EN, VM_CMD_EN); > + mtk_dsi_mask(dsi, dsi->driver_data->reg_vm_cmd_off, TS_VFP_EN, TS_VFP_EN); > } > > static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) > @@ -714,7 +716,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > > if (dsi->driver_data->has_shadow_ctl) > writel(FORCE_COMMIT | BYPASS_SHADOW, > - dsi->regs + DSI_SHADOW_DEBUG); > + dsi->regs + dsi->driver_data->reg_shadow_dbg_off); > > mtk_dsi_reset_engine(dsi); > mtk_dsi_phy_timconfig(dsi); > @@ -1263,26 +1265,36 @@ static void mtk_dsi_remove(struct platform_device *pdev) > > static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = { > .reg_cmdq_off = 0x200, > + .reg_vm_cmd_off = 0x130, > + .reg_shadow_dbg_off = 0x190 > }; > > static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = { > .reg_cmdq_off = 0x180, > + .reg_vm_cmd_off = 0x130, > + .reg_shadow_dbg_off = 0x190 > }; > > static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = { > .reg_cmdq_off = 0x200, > + .reg_vm_cmd_off = 0x130, > + .reg_shadow_dbg_off = 0x190, > .has_shadow_ctl = true, > .has_size_ctl = true, > }; > > static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = { > .reg_cmdq_off = 0xd00, > + .reg_vm_cmd_off = 0x200, > + .reg_shadow_dbg_off = 0xc00, > .has_shadow_ctl = true, > .has_size_ctl = true, > }; > > static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = { > .reg_cmdq_off = 0xd00, > + .reg_vm_cmd_off = 0x200, > + .reg_shadow_dbg_off = 0xc00, > .has_shadow_ctl = true, > .has_size_ctl = true, > .cmdq_long_packet_ctl = true, > -- > 2.47.0 >
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index e61b9bc68e9a..978332cd52f5 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -139,11 +139,11 @@ #define CLK_HS_POST GENMASK(15, 8) #define CLK_HS_EXIT GENMASK(23, 16) -#define DSI_VM_CMD_CON 0x130 +/* DSI_VM_CMD_CON */ #define VM_CMD_EN BIT(0) #define TS_VFP_EN BIT(5) -#define DSI_SHADOW_DEBUG 0x190U +/* DSI_SHADOW_DEBUG */ #define FORCE_COMMIT BIT(0) #define BYPASS_SHADOW BIT(1) @@ -187,6 +187,8 @@ struct phy; struct mtk_dsi_driver_data { const u32 reg_cmdq_off; + const u32 reg_vm_cmd_off; + const u32 reg_shadow_dbg_off; bool has_shadow_ctl; bool has_size_ctl; bool cmdq_long_packet_ctl; @@ -367,8 +369,8 @@ static void mtk_dsi_set_mode(struct mtk_dsi *dsi) static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) { - mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN); - mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); + mtk_dsi_mask(dsi, dsi->driver_data->reg_vm_cmd_off, VM_CMD_EN, VM_CMD_EN); + mtk_dsi_mask(dsi, dsi->driver_data->reg_vm_cmd_off, TS_VFP_EN, TS_VFP_EN); } static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) @@ -714,7 +716,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) if (dsi->driver_data->has_shadow_ctl) writel(FORCE_COMMIT | BYPASS_SHADOW, - dsi->regs + DSI_SHADOW_DEBUG); + dsi->regs + dsi->driver_data->reg_shadow_dbg_off); mtk_dsi_reset_engine(dsi); mtk_dsi_phy_timconfig(dsi); @@ -1263,26 +1265,36 @@ static void mtk_dsi_remove(struct platform_device *pdev) static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = { .reg_cmdq_off = 0x200, + .reg_vm_cmd_off = 0x130, + .reg_shadow_dbg_off = 0x190 }; static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = { .reg_cmdq_off = 0x180, + .reg_vm_cmd_off = 0x130, + .reg_shadow_dbg_off = 0x190 }; static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = { .reg_cmdq_off = 0x200, + .reg_vm_cmd_off = 0x130, + .reg_shadow_dbg_off = 0x190, .has_shadow_ctl = true, .has_size_ctl = true, }; static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = { .reg_cmdq_off = 0xd00, + .reg_vm_cmd_off = 0x200, + .reg_shadow_dbg_off = 0xc00, .has_shadow_ctl = true, .has_size_ctl = true, }; static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = { .reg_cmdq_off = 0xd00, + .reg_vm_cmd_off = 0x200, + .reg_shadow_dbg_off = 0xc00, .has_shadow_ctl = true, .has_size_ctl = true, .cmdq_long_packet_ctl = true,
Registers DSI_VM_CMD and DSI_SHADOW_DEBUG start at different addresses in both MT8186 and MT8188 compared to the older IPs. Add two members in struct mtk_dsi_driver_data to specify the offsets for these two registers on a per-SoC basis, then do specify those in all of the currently present SoC driver data. This fixes writes to the Video Mode Command Packet Control register, fixing enablement of command packet transmission (VM_CMD_EN) and allowance of this transmission during the VFP period (TS_VFP_EN) on both MT8186 and MT8188. Fixes: 03d7adc41027 ("drm/mediatek: Add mt8186 dsi compatible to mtk_dsi.c") Fixes: 814d5341f314 ("drm/mediatek: Add mt8188 dsi compatible to mtk_dsi.c") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/gpu/drm/mediatek/mtk_dsi.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-)