| Message ID | 20250103060035.30688-2-jianjun.wang@mediatek.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: mediatek-gen3: Add MT8196 support | expand |
On Fri, Jan 03, 2025 at 02:00:11PM +0800, Jianjun Wang wrote: > + clock-names: > + items: > + - const: pl_250m > + - const: tl_26m > + - const: peri_26m > + - const: peri_mem > + - const: ahb_apb > + - const: low_power > + > + resets: > + minItems: 1 > + maxItems: 2 > + > + reset-names: > + minItems: 1 > + maxItems: 2 Why resets are flexible? Best regards, Krzysztof
Il 03/01/25 07:00, Jianjun Wang ha scritto: > Add compatible string and clock definition for MT8196. It has 6 clocks like > the MT8195, but 2 of them are different. > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > --- > .../bindings/pci/mediatek-pcie-gen3.yaml | 29 +++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > index f05aab2b1add..b4158a666fb6 100644 > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > @@ -51,6 +51,7 @@ properties: > - mediatek,mt7986-pcie > - mediatek,mt8188-pcie > - mediatek,mt8195-pcie > + - mediatek,mt8196-pcie > - const: mediatek,mt8192-pcie > - const: mediatek,mt8192-pcie > - const: airoha,en7581-pcie > @@ -197,6 +198,34 @@ allOf: > minItems: 1 > maxItems: 2 > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - mediatek,mt8196-pcie > + then: > + properties: > + clocks: > + minItems: 6 > + > + clock-names: > + items: > + - const: pl_250m > + - const: tl_26m > + - const: peri_26m > + - const: peri_mem > + - const: ahb_apb ahb_apb is a bus clock, so you can set it as - const: bus > + - const: low_power Can you please clarify what the LP clock is for? Thanks, Angelo > + > + resets: > + minItems: 1 > + maxItems: 2 > + > + reset-names: > + minItems: 1 > + maxItems: 2 > + > - if: > properties: > compatible:
On Fri, 2025-01-03 at 10:26 +0100, AngeloGioacchino Del Regno wrote: > External email : Please do not click links or open attachments until > you have verified the sender or the content. > > > Il 03/01/25 07:00, Jianjun Wang ha scritto: > > Add compatible string and clock definition for MT8196. It has 6 > > clocks like > > the MT8195, but 2 of them are different. > > > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > > --- > > .../bindings/pci/mediatek-pcie-gen3.yaml | 29 > > +++++++++++++++++++ > > 1 file changed, 29 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie- > > gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie- > > gen3.yaml > > index f05aab2b1add..b4158a666fb6 100644 > > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > @@ -51,6 +51,7 @@ properties: > > - mediatek,mt7986-pcie > > - mediatek,mt8188-pcie > > - mediatek,mt8195-pcie > > + - mediatek,mt8196-pcie > > - const: mediatek,mt8192-pcie > > - const: mediatek,mt8192-pcie > > - const: airoha,en7581-pcie > > @@ -197,6 +198,34 @@ allOf: > > minItems: 1 > > maxItems: 2 > > > > + - if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - mediatek,mt8196-pcie > > + then: > > + properties: > > + clocks: > > + minItems: 6 > > + > > + clock-names: > > + items: > > + - const: pl_250m > > + - const: tl_26m > > + - const: peri_26m > > + - const: peri_mem > > + - const: ahb_apb > > ahb_apb is a bus clock, so you can set it as > > - const: bus Agree, I'll change it to "bus" in the next version, thanks. > > > > + - const: low_power > > Can you please clarify what the LP clock is for? This is a power-saving clock. Its clock source consumes less power than a regular clock, we need to keep this clock on if when entering L1.2 during suspend. Thanks. > > Thanks, > Angelo > > > + > > + resets: > > + minItems: 1 > > + maxItems: 2 > > + > > + reset-names: > > + minItems: 1 > > + maxItems: 2 > > + > > - if: > > properties: > > compatible: > >
On Fri, 2025-01-03 at 10:10 +0100, Krzysztof Kozlowski wrote: > External email : Please do not click links or open attachments until > you have verified the sender or the content. > > > On Fri, Jan 03, 2025 at 02:00:11PM +0800, Jianjun Wang wrote: > > + clock-names: > > + items: > > + - const: pl_250m > > + - const: tl_26m > > + - const: peri_26m > > + - const: peri_mem > > + - const: ahb_apb > > + - const: low_power > > + > > + resets: > > + minItems: 1 > > + maxItems: 2 > > + > > + reset-names: > > + minItems: 1 > > + maxItems: 2 > > Why resets are flexible? There are two resets, one for MAC and another for PHY, some platforms may only use one of them. Would you prefer to set the number of resets to a fixed value for specific platforms? Thanks. > > Best regards, > Krzysztof > >
On 06/01/2025 10:26, Jianjun Wang (王建军) wrote: > On Fri, 2025-01-03 at 10:10 +0100, Krzysztof Kozlowski wrote: >> External email : Please do not click links or open attachments until >> you have verified the sender or the content. >> >> >> On Fri, Jan 03, 2025 at 02:00:11PM +0800, Jianjun Wang wrote: >>> + clock-names: >>> + items: >>> + - const: pl_250m >>> + - const: tl_26m >>> + - const: peri_26m >>> + - const: peri_mem >>> + - const: ahb_apb >>> + - const: low_power >>> + >>> + resets: >>> + minItems: 1 >>> + maxItems: 2 >>> + >>> + reset-names: >>> + minItems: 1 >>> + maxItems: 2 >> >> Why resets are flexible? > > There are two resets, one for MAC and another for PHY, some platforms > may only use one of them. Even more questions. What does it mean use? Is it there or is it not? Platform like SoC? But this is one specific SoC, it cannot be used on different SoC. > > Would you prefer to set the number of resets to a fixed value for > specific platforms? Everything should be constrained to match hardware. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index f05aab2b1add..b4158a666fb6 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -51,6 +51,7 @@ properties: - mediatek,mt7986-pcie - mediatek,mt8188-pcie - mediatek,mt8195-pcie + - mediatek,mt8196-pcie - const: mediatek,mt8192-pcie - const: mediatek,mt8192-pcie - const: airoha,en7581-pcie @@ -197,6 +198,34 @@ allOf: minItems: 1 maxItems: 2 + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8196-pcie + then: + properties: + clocks: + minItems: 6 + + clock-names: + items: + - const: pl_250m + - const: tl_26m + - const: peri_26m + - const: peri_mem + - const: ahb_apb + - const: low_power + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + maxItems: 2 + - if: properties: compatible:
Add compatible string and clock definition for MT8196. It has 6 clocks like the MT8195, but 2 of them are different. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> --- .../bindings/pci/mediatek-pcie-gen3.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+)