Message ID | 20250106173734.412353-1-dbarboza@ventanamicro.com (mailing list archive) |
---|---|
Headers | show |
Series | target/riscv: add traces for exceptions | expand |
On Tue, Jan 7, 2025 at 3:38 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > Hi, > > This new version is a re-sent of v1, rebased on top of > alistair/riscv-to-apply.next, with acks/r-bs added. > > No other changes made. > > Changes from v1: > - rebased on top of alistair/riscv-to-apply.next > - v1 link: https://lore.kernel.org/qemu-riscv/20241219174657.1988767-1-dbarboza@ventanamicro.com/ > > Daniel Henrique Barboza (2): > target/riscv: use RISCVException enum in exception helpers > target/riscv: add trace in riscv_raise_exception() Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.h | 3 ++- > target/riscv/op_helper.c | 9 ++++++++- > target/riscv/trace-events | 3 +++ > target/riscv/translate.c | 2 +- > 4 files changed, 14 insertions(+), 3 deletions(-) > > -- > 2.47.1 > >