| Message ID | 20250106123122.3531845-2-c-vankar@ti.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add bootph-all property to necessary nodes to enable ethernet boot for AM68-SK, J722s and AM62p-SK | expand |
On 06/01/2025 14:31, Chintan Vankar wrote: > Ethernet boot requires CPSW nodes to be present starting from R5 SPL > stage. Add bootph-all property to necessary nodes for CPSW to enable those > nodes during SPL stage along with later boot stages for AM68-SK. > > Signed-off-by: Chintan Vankar <c-vankar@ti.com> Reviewed-by: Roger Quadros <rogerq@@kernel.org>
On 06/01/2025 14:31, Chintan Vankar wrote: > Ethernet boot requires CPSW nodes to be present starting from R5 SPL > stage. Add bootph-all property to necessary nodes for CPSW to enable those > nodes during SPL stage along with later boot stages for AM68-SK. > > Signed-off-by: Chintan Vankar <c-vankar@ti.com> > --- > arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 5 +++++ > arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 ++ > 2 files changed, 7 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts > index 11522b36e0ce..f1f8b228926d 100644 > --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts > +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts > @@ -333,6 +333,7 @@ J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ > J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ > J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ > >; > + bootph-all; Shouldn't bootph-all be the first property in the DT nodes? > }; > > mcu_mdio_pins_default: mcu-mdio-default-pins { > @@ -340,6 +341,7 @@ mcu_mdio_pins_default: mcu-mdio-default-pins { > J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ > J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ > >; > + bootph-all; > }; > > mcu_mcan0_pins_default: mcu-mcan0-default-pins { > @@ -610,11 +612,13 @@ &main_sdhci1 { > &mcu_cpsw { > pinctrl-names = "default"; > pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; > + bootph-all; > }; > > &davinci_mdio { > phy0: ethernet-phy@0 { > reg = <0>; > + bootph-all; > ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; > ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > ti,min-output-impedance; > @@ -624,6 +628,7 @@ phy0: ethernet-phy@0 { > &cpsw_port1 { > phy-mode = "rgmii-rxid"; > phy-handle = <&phy0>; > + bootph-all; > }; > > &mcu_mcan0 { > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi > index bc31266126d0..cfae226d3c63 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi > @@ -154,12 +154,14 @@ mcu_conf: bus@40f00000 { > cpsw_mac_syscon: ethernet-mac-syscon@200 { > compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; > reg = <0x200 0x8>; > + bootph-all; > }; > > phy_gmii_sel: phy@4040 { > compatible = "ti,am654-phy-gmii-sel"; > reg = <0x4040 0x4>; > #phy-cells = <1>; > + bootph-all; > }; > > };
diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 11522b36e0ce..f1f8b228926d 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -333,6 +333,7 @@ J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ >; + bootph-all; }; mcu_mdio_pins_default: mcu-mdio-default-pins { @@ -340,6 +341,7 @@ mcu_mdio_pins_default: mcu-mdio-default-pins { J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ >; + bootph-all; }; mcu_mcan0_pins_default: mcu-mcan0-default-pins { @@ -610,11 +612,13 @@ &main_sdhci1 { &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; + bootph-all; }; &davinci_mdio { phy0: ethernet-phy@0 { reg = <0>; + bootph-all; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; ti,min-output-impedance; @@ -624,6 +628,7 @@ phy0: ethernet-phy@0 { &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&phy0>; + bootph-all; }; &mcu_mcan0 { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index bc31266126d0..cfae226d3c63 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -154,12 +154,14 @@ mcu_conf: bus@40f00000 { cpsw_mac_syscon: ethernet-mac-syscon@200 { compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; reg = <0x200 0x8>; + bootph-all; }; phy_gmii_sel: phy@4040 { compatible = "ti,am654-phy-gmii-sel"; reg = <0x4040 0x4>; #phy-cells = <1>; + bootph-all; }; };
Ethernet boot requires CPSW nodes to be present starting from R5 SPL stage. Add bootph-all property to necessary nodes for CPSW to enable those nodes during SPL stage along with later boot stages for AM68-SK. Signed-off-by: Chintan Vankar <c-vankar@ti.com> --- arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 5 +++++ arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 ++ 2 files changed, 7 insertions(+)