| Message ID | 20250110-topic-sm8650-ddr-bw-scaling-v1-0-041d836b084c@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | arm64: qcom: sm8650: add DDR, LLCC & L3 CPU bandwidth scaling | expand |
On Fri, 10 Jan 2025 16:21:17 +0100, Neil Armstrong wrote: > Add the OSM L3 controller node then add the necessary interconnect > properties with the appropriate OPP table for each CPU cluster to > allow the DDR, LLCC & L3 CPU bandwidth to scale along the CPU > cluster operating point. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > Neil Armstrong (4): > dt-bindings: interconnect: OSM L3: Document sm8650 OSM L3 compatible > arm64: dts: qcom: sm8650: add OSM L3 node > arm64: dts: qcom: sm8650: add cpu interconnect nodes > arm64: dts: qcom: add cpu OPP table with DDR, LLCC & L3 bandwidths > > .../bindings/interconnect/qcom,osm-l3.yaml | 1 + > arch/arm64/boot/dts/qcom/sm8650.dtsi | 938 +++++++++++++++++++++ > 2 files changed, 939 insertions(+) > --- > base-commit: 6ecd20965bdc21b265a0671ccf36d9ad8043f5ab > change-id: 20250110-topic-sm8650-ddr-bw-scaling-f1863fb91246 > > Best regards, > -- > Neil Armstrong <neil.armstrong@linaro.org> > > > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20250110-topic-sm8650-ddr-bw-scaling-v1-0-041d836b084c@linaro.org: arch/arm64/boot/dts/qcom/sm8650-hdk.dtb: display-subsystem@ae00000: interconnects: [[213, 3, 7, 8, 1, 7]] is too short from schema $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml# arch/arm64/boot/dts/qcom/sm8650-mtp.dtb: display-subsystem@ae00000: interconnects: [[196, 3, 7, 8, 1, 7]] is too short from schema $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml# arch/arm64/boot/dts/qcom/sm8650-qrd.dtb: display-subsystem@ae00000: interconnects: [[205, 3, 7, 8, 1, 7]] is too short from schema $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml#
Add the OSM L3 controller node then add the necessary interconnect properties with the appropriate OPP table for each CPU cluster to allow the DDR, LLCC & L3 CPU bandwidth to scale along the CPU cluster operating point. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Neil Armstrong (4): dt-bindings: interconnect: OSM L3: Document sm8650 OSM L3 compatible arm64: dts: qcom: sm8650: add OSM L3 node arm64: dts: qcom: sm8650: add cpu interconnect nodes arm64: dts: qcom: add cpu OPP table with DDR, LLCC & L3 bandwidths .../bindings/interconnect/qcom,osm-l3.yaml | 1 + arch/arm64/boot/dts/qcom/sm8650.dtsi | 938 +++++++++++++++++++++ 2 files changed, 939 insertions(+) --- base-commit: 6ecd20965bdc21b265a0671ccf36d9ad8043f5ab change-id: 20250110-topic-sm8650-ddr-bw-scaling-f1863fb91246 Best regards,