| Message ID | 20250107141015.3367194-5-rrichter@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | cxl: Add address translation support and enable AMD Zen5 platforms | expand |
On Tue, Jan 07, 2025 at 03:09:50PM +0100, Robert Richter wrote: > There are various configuration cases of HDM decoder registers causing > different code paths. Add comments to cxl_hdm_decode_init() to better > explain them. > > Signed-off-by: Robert Richter <rrichter@amd.com> > --- > drivers/cxl/core/pci.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > This addresses some of my prior questions, but I still think this function is worth some extra scrutiny. Reviewed-by: Gregory Price <gourry@gourry.net> > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index c7050c13f71a..4d2154457efb 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -416,9 +416,17 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, > if (global_ctrl & CXL_HDM_DECODER_ENABLE || (!hdm && info->mem_enabled)) > return devm_cxl_enable_mem(&port->dev, cxlds); > > + /* > + * If the HDM Decoder Capability does not exist and DVSEC was > + * not setup, the DVSEC based emulation cannot be used. > + */ > if (!hdm) > return -ENODEV; > > + /* > + * The HDM Decoder Capability exists but is globally disabled. > + */ > + > /* > * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base > * [High,Low] when HDM operation is enabled the range register values > @@ -426,7 +434,8 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, > * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges > * are expected even though Linux does not require or maintain that > * match. If at least one DVSEC range is enabled and allowed, skip HDM > - * Decoder Capability Enable. > + * Decoder Capability Enable. Else, use the HDM Decoder Capability and > + * enable it. > */ > if (!info->mem_enabled) { > rc = devm_cxl_enable_hdm(&port->dev, cxlhdm); > -- > 2.39.5 >
On Tue, 7 Jan 2025 11:51:23 -0500 Gregory Price <gourry@gourry.net> wrote: > On Tue, Jan 07, 2025 at 03:09:50PM +0100, Robert Richter wrote: > > There are various configuration cases of HDM decoder registers causing > > different code paths. Add comments to cxl_hdm_decode_init() to better > > explain them. > > > > Signed-off-by: Robert Richter <rrichter@amd.com> > > --- > > drivers/cxl/core/pci.c | 11 ++++++++++- > > 1 file changed, 10 insertions(+), 1 deletion(-) > > > > This addresses some of my prior questions, but I still think this > function is worth some extra scrutiny. > > Reviewed-by: Gregory Price <gourry@gourry.net> Definitely an improvement. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > > index c7050c13f71a..4d2154457efb 100644 > > --- a/drivers/cxl/core/pci.c > > +++ b/drivers/cxl/core/pci.c > > @@ -416,9 +416,17 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, > > if (global_ctrl & CXL_HDM_DECODER_ENABLE || (!hdm && info->mem_enabled)) > > return devm_cxl_enable_mem(&port->dev, cxlds); > > > > + /* > > + * If the HDM Decoder Capability does not exist and DVSEC was > > + * not setup, the DVSEC based emulation cannot be used. > > + */ > > if (!hdm) > > return -ENODEV; > > > > + /* > > + * The HDM Decoder Capability exists but is globally disabled. > > + */ > > + > > /* > > * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base > > * [High,Low] when HDM operation is enabled the range register values > > @@ -426,7 +434,8 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, > > * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges > > * are expected even though Linux does not require or maintain that > > * match. If at least one DVSEC range is enabled and allowed, skip HDM > > - * Decoder Capability Enable. > > + * Decoder Capability Enable. Else, use the HDM Decoder Capability and > > + * enable it. > > */ > > if (!info->mem_enabled) { > > rc = devm_cxl_enable_hdm(&port->dev, cxlhdm); > > -- > > 2.39.5 > >
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index c7050c13f71a..4d2154457efb 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -416,9 +416,17 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, if (global_ctrl & CXL_HDM_DECODER_ENABLE || (!hdm && info->mem_enabled)) return devm_cxl_enable_mem(&port->dev, cxlds); + /* + * If the HDM Decoder Capability does not exist and DVSEC was + * not setup, the DVSEC based emulation cannot be used. + */ if (!hdm) return -ENODEV; + /* + * The HDM Decoder Capability exists but is globally disabled. + */ + /* * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base * [High,Low] when HDM operation is enabled the range register values @@ -426,7 +434,8 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges * are expected even though Linux does not require or maintain that * match. If at least one DVSEC range is enabled and allowed, skip HDM - * Decoder Capability Enable. + * Decoder Capability Enable. Else, use the HDM Decoder Capability and + * enable it. */ if (!info->mem_enabled) { rc = devm_cxl_enable_hdm(&port->dev, cxlhdm);
There are various configuration cases of HDM decoder registers causing different code paths. Add comments to cxl_hdm_decode_init() to better explain them. Signed-off-by: Robert Richter <rrichter@amd.com> --- drivers/cxl/core/pci.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)