| Message ID | 20250113-mdssdt_qcs8300-v3-3-6c8e93459600@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Display enablement changes for Qualcomm QCS8300 platform | expand |
On Mon, Jan 13, 2025 at 04:03:10PM +0800, Yongxing Mou wrote: > +patternProperties: > + "^display-controller@[0-9a-f]+$": > + type: object > + additionalProperties: true > + > + properties: > + compatible: > + items: > + - const: qcom,qcs8300-dpu > + - const: qcom,sa8775p-dpu > + > + "^displayport-controller@[0-9a-f]+$": > + type: object > + additionalProperties: true > + > + properties: > + compatible: > + items: > + - const: qcom,qcs8300-dp > + - const: qcom,sm8650-dp Parts of qcs8300 display are compatible with sa8775p, other parts with sm8650. That's odd or even not correct. Assuming it is actually correct, it deserves explanation in commit msg. Best regards, Krzysztof
On Tue, 14 Jan 2025 at 09:57, Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On Mon, Jan 13, 2025 at 04:03:10PM +0800, Yongxing Mou wrote: > > +patternProperties: > > + "^display-controller@[0-9a-f]+$": > > + type: object > > + additionalProperties: true > > + > > + properties: > > + compatible: > > + items: > > + - const: qcom,qcs8300-dpu > > + - const: qcom,sa8775p-dpu > > + > > + "^displayport-controller@[0-9a-f]+$": > > + type: object > > + additionalProperties: true > > + > > + properties: > > + compatible: > > + items: > > + - const: qcom,qcs8300-dp > > + - const: qcom,sm8650-dp > > Parts of qcs8300 display are compatible with sa8775p, other parts with > sm8650. That's odd or even not correct. Assuming it is actually correct, > it deserves explanation in commit msg. It seems to be correct. These are two different IP blocks with different modifications. QCS8300's DP configuration matches the SM8650 ([1]), though the DPU is the same as the one on the SA8775P platform. [1] https://lore.kernel.org/dri-devel/411626da-7563-48fb-ac7c-94f06e73e4b8@quicinc.com/
On 14/01/2025 11:00, Dmitry Baryshkov wrote: > On Tue, 14 Jan 2025 at 09:57, Krzysztof Kozlowski <krzk@kernel.org> wrote: >> >> On Mon, Jan 13, 2025 at 04:03:10PM +0800, Yongxing Mou wrote: >>> +patternProperties: >>> + "^display-controller@[0-9a-f]+$": >>> + type: object >>> + additionalProperties: true >>> + >>> + properties: >>> + compatible: >>> + items: >>> + - const: qcom,qcs8300-dpu >>> + - const: qcom,sa8775p-dpu >>> + >>> + "^displayport-controller@[0-9a-f]+$": >>> + type: object >>> + additionalProperties: true >>> + >>> + properties: >>> + compatible: >>> + items: >>> + - const: qcom,qcs8300-dp >>> + - const: qcom,sm8650-dp >> >> Parts of qcs8300 display are compatible with sa8775p, other parts with >> sm8650. That's odd or even not correct. Assuming it is actually correct, >> it deserves explanation in commit msg. > > It seems to be correct. These are two different IP blocks with > different modifications. QCS8300's DP configuration matches the SM8650 > ([1]), though the DPU is the same as the one on the SA8775P platform. > > [1] https://lore.kernel.org/dri-devel/411626da-7563-48fb-ac7c-94f06e73e4b8@quicinc.com/ That's the driver, so you claim that qcs8300, which is a sa8775p, is not compatible with sa8775p because of current driver code? You see the contradiction? sa8775p is not compatible with sa8775p because of current driver patch? I don't think it is correct, but let's repeat: if you think otherwise, this should be explain in commit msg. Best regards, Krzysztof
On Tue, Jan 14, 2025 at 11:11:23AM +0100, Krzysztof Kozlowski wrote: > On 14/01/2025 11:00, Dmitry Baryshkov wrote: > > On Tue, 14 Jan 2025 at 09:57, Krzysztof Kozlowski <krzk@kernel.org> wrote: > >> > >> On Mon, Jan 13, 2025 at 04:03:10PM +0800, Yongxing Mou wrote: > >>> +patternProperties: > >>> + "^display-controller@[0-9a-f]+$": > >>> + type: object > >>> + additionalProperties: true > >>> + > >>> + properties: > >>> + compatible: > >>> + items: > >>> + - const: qcom,qcs8300-dpu > >>> + - const: qcom,sa8775p-dpu > >>> + > >>> + "^displayport-controller@[0-9a-f]+$": > >>> + type: object > >>> + additionalProperties: true > >>> + > >>> + properties: > >>> + compatible: > >>> + items: > >>> + - const: qcom,qcs8300-dp > >>> + - const: qcom,sm8650-dp > >> > >> Parts of qcs8300 display are compatible with sa8775p, other parts with > >> sm8650. That's odd or even not correct. Assuming it is actually correct, > >> it deserves explanation in commit msg. > > > > It seems to be correct. These are two different IP blocks with > > different modifications. QCS8300's DP configuration matches the SM8650 > > ([1]), though the DPU is the same as the one on the SA8775P platform. > > > > [1] https://lore.kernel.org/dri-devel/411626da-7563-48fb-ac7c-94f06e73e4b8@quicinc.com/ > > That's the driver, so you claim that qcs8300, which is a sa8775p, is not > compatible with sa8775p because of current driver code? You see the > contradiction? sa8775p is not compatible with sa8775p because of current > driver patch? I think you are slightly confused with different similar QCS SKUs here. QCS9100 is sa8775p. QCS8300 is a lighter version of it. > > I don't think it is correct, but let's repeat: if you think otherwise, > this should be explain in commit msg. > > Best regards, > Krzysztof
On 14/01/2025 12:09, Dmitry Baryshkov wrote: > On Tue, Jan 14, 2025 at 11:11:23AM +0100, Krzysztof Kozlowski wrote: >> On 14/01/2025 11:00, Dmitry Baryshkov wrote: >>> On Tue, 14 Jan 2025 at 09:57, Krzysztof Kozlowski <krzk@kernel.org> wrote: >>>> >>>> On Mon, Jan 13, 2025 at 04:03:10PM +0800, Yongxing Mou wrote: >>>>> +patternProperties: >>>>> + "^display-controller@[0-9a-f]+$": >>>>> + type: object >>>>> + additionalProperties: true >>>>> + >>>>> + properties: >>>>> + compatible: >>>>> + items: >>>>> + - const: qcom,qcs8300-dpu >>>>> + - const: qcom,sa8775p-dpu >>>>> + >>>>> + "^displayport-controller@[0-9a-f]+$": >>>>> + type: object >>>>> + additionalProperties: true >>>>> + >>>>> + properties: >>>>> + compatible: >>>>> + items: >>>>> + - const: qcom,qcs8300-dp >>>>> + - const: qcom,sm8650-dp >>>> >>>> Parts of qcs8300 display are compatible with sa8775p, other parts with >>>> sm8650. That's odd or even not correct. Assuming it is actually correct, >>>> it deserves explanation in commit msg. >>> >>> It seems to be correct. These are two different IP blocks with >>> different modifications. QCS8300's DP configuration matches the SM8650 >>> ([1]), though the DPU is the same as the one on the SA8775P platform. >>> >>> [1] https://lore.kernel.org/dri-devel/411626da-7563-48fb-ac7c-94f06e73e4b8@quicinc.com/ >> >> That's the driver, so you claim that qcs8300, which is a sa8775p, is not >> compatible with sa8775p because of current driver code? You see the >> contradiction? sa8775p is not compatible with sa8775p because of current >> driver patch? > > I think you are slightly confused with different similar QCS SKUs here. > QCS9100 is sa8775p. QCS8300 is a lighter version of it. True, yet still qcs8300 derives from SA8775p: https://lore.kernel.org/all/acdf1267-ce56-4ec1-8407-a5f3212a8bfe@quicinc.com/ Therefore my comment, that commit msg must explain why derivative display is SA8775p-compatible in DPU part, but not in DP part, is still valid. Look how useful is commit msg here: "Document the MDSS hardware found on the Qualcomm QCS8300 platform." It says exactly what is in the diff. As well we could just skip it... Best regards, Krzysztof
On 2025/1/14 18:11, Krzysztof Kozlowski wrote: > On 14/01/2025 11:00, Dmitry Baryshkov wrote: >> On Tue, 14 Jan 2025 at 09:57, Krzysztof Kozlowski <krzk@kernel.org> wrote: >>> >>> On Mon, Jan 13, 2025 at 04:03:10PM +0800, Yongxing Mou wrote: >>>> +patternProperties: >>>> + "^display-controller@[0-9a-f]+$": >>>> + type: object >>>> + additionalProperties: true >>>> + >>>> + properties: >>>> + compatible: >>>> + items: >>>> + - const: qcom,qcs8300-dpu >>>> + - const: qcom,sa8775p-dpu >>>> + >>>> + "^displayport-controller@[0-9a-f]+$": >>>> + type: object >>>> + additionalProperties: true >>>> + >>>> + properties: >>>> + compatible: >>>> + items: >>>> + - const: qcom,qcs8300-dp >>>> + - const: qcom,sm8650-dp >>> >>> Parts of qcs8300 display are compatible with sa8775p, other parts with >>> sm8650. That's odd or even not correct. Assuming it is actually correct, >>> it deserves explanation in commit msg. >> >> It seems to be correct. These are two different IP blocks with >> different modifications. QCS8300's DP configuration matches the SM8650 >> ([1]), though the DPU is the same as the one on the SA8775P platform. >> >> [1] https://lore.kernel.org/dri-devel/411626da-7563-48fb-ac7c-94f06e73e4b8@quicinc.com/ > > That's the driver, so you claim that qcs8300, which is a sa8775p, is not > compatible with sa8775p because of current driver code? You see the > contradiction? sa8775p is not compatible with sa8775p because of current > driver patch? > > I don't think it is correct, but let's repeat: if you think otherwise, > this should be explain in commit msg. > > Best regards, > Krzysztof Hi,let me explain this: qcs8300 uses the same DPU as sa8775p, which is DPU_8_4. Therefore, for the DPU driver, qcs8300 reuses the driver of sa8775p. However, for the DisplayPort controller of qcs8300, it's different with sa8775p. qcs8300 only supports one DisplayPort output port, while sa8775p has two DPUs and supports four DisplayPort outputs. Therefore, the DisplayPort controller driver of sa8775p cannot be reused for qcs8300. Additionally, the base offset of qcs8300's DisplayPort controller is the same as that of sm8650, so the DisplayPort controller reuses "qcom,sm8650-dp". I explained this in the commit messages of the previous two bindings, but it might not have been explained in the commit message of this patch.i will update the commit msg in next patchset.
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml new file mode 100644 index 0000000000000000000000000000000000000000..eb7f36387f748793ebf662baded4a13a61b3ce39 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml @@ -0,0 +1,244 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,qcs8300-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QCS8300 Display MDSS + +maintainers: + - Yongxing Mou <quic_yongmou@quicinc.com> + +description: + QCS8300 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DP interfaces and EDP etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,qcs8300-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 3 + + interconnect-names: + maxItems: 3 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,qcs8300-dpu + - const: qcom,sa8775p-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,qcs8300-dp + - const: qcom,sm8650-dp + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,qcs8300-gcc.h> + #include <dt-bindings/clock/qcom,sa8775p-dispcc.h> + #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + mdss: display-subsystem@ae00000 { + compatible = "qcom,qcs8300-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + resets = <&dispcc_core_bcr>; + power-domains = <&dispcc_gdsc>; + + clocks = <&dispcc_ahb_clk>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc_mdp_clk>; + + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x1000 0x402>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,qcs8300-dpu", "qcom,sa8775p-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + displayport-controller@af54000 { + compatible = "qcom,qcs8300-dp", "qcom,sm8650-dp"; + + pinctrl-0 = <&dp_hot_plug_det>; + pinctrl-names = "default"; + + reg = <0xaf54000 0x104>, + <0xaf54200 0x0c0>, + <0xaf55000 0x770>, + <0xaf56000 0x09c>, + <0xaf57000 0x09c>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; + phys = <&mdss_edp_phy>; + phy-names = "dp"; + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; +...
Document the MDSS hardware found on the Qualcomm QCS8300 platform. Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com> --- .../bindings/display/msm/qcom,qcs8300-mdss.yaml | 244 +++++++++++++++++++++ 1 file changed, 244 insertions(+)