| Message ID | 20250114093647.4952-2-jason.chien@sifive.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [1/2] hw/riscv/riscv-iommu: Remove redundant variables | expand |
On 1/14/25 6:36 AM, Jason Chien wrote: > Signed-off-by: Jason Chien <jason.chien@sifive.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > hw/riscv/riscv-iommu-bits.h | 22 ++++++---------------- > 1 file changed, 6 insertions(+), 16 deletions(-) > > diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h > index 485f36b9c9..de599b80d6 100644 > --- a/hw/riscv/riscv-iommu-bits.h > +++ b/hw/riscv/riscv-iommu-bits.h > @@ -50,8 +50,14 @@ struct riscv_iommu_pq_record { > #define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33) > #define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34) > #define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40) > + > /* Payload fields */ > +#define RISCV_IOMMU_PREQ_PAYLOAD_R BIT_ULL(0) > +#define RISCV_IOMMU_PREQ_PAYLOAD_W BIT_ULL(1) > +#define RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2) > #define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0) > +#define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3) > +#define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12) > > /* Common field positions */ > #define RISCV_IOMMU_PPN_FIELD GENMASK_ULL(53, 10) > @@ -382,22 +388,6 @@ enum riscv_iommu_fq_ttypes { > RISCV_IOMMU_FW_TTYPE_PCIE_MSG_REQ = 9, > }; > > -/* Header fields */ > -#define RISCV_IOMMU_PREQ_HDR_PID GENMASK_ULL(31, 12) > -#define RISCV_IOMMU_PREQ_HDR_PV BIT_ULL(32) > -#define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33) > -#define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34) > -#define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40) > - > -/* Payload fields */ > -#define RISCV_IOMMU_PREQ_PAYLOAD_R BIT_ULL(0) > -#define RISCV_IOMMU_PREQ_PAYLOAD_W BIT_ULL(1) > -#define RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2) > -#define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0) > -#define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3) > -#define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12) > - > - > /* > * struct riscv_iommu_msi_pte - MSI Page Table Entry > */
On Tue, Jan 14, 2025 at 05:36:46PM +0800, Jason Chien wrote: > Signed-off-by: Jason Chien <jason.chien@sifive.com> > --- > hw/riscv/riscv-iommu-bits.h | 22 ++++++---------------- > 1 file changed, 6 insertions(+), 16 deletions(-) > > diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h > index 485f36b9c9..de599b80d6 100644 > --- a/hw/riscv/riscv-iommu-bits.h > +++ b/hw/riscv/riscv-iommu-bits.h > @@ -50,8 +50,14 @@ struct riscv_iommu_pq_record { > #define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33) > #define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34) > #define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40) > + > /* Payload fields */ > +#define RISCV_IOMMU_PREQ_PAYLOAD_R BIT_ULL(0) > +#define RISCV_IOMMU_PREQ_PAYLOAD_W BIT_ULL(1) > +#define RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2) > #define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0) > +#define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3) > +#define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12) > > /* Common field positions */ > #define RISCV_IOMMU_PPN_FIELD GENMASK_ULL(53, 10) > @@ -382,22 +388,6 @@ enum riscv_iommu_fq_ttypes { > RISCV_IOMMU_FW_TTYPE_PCIE_MSG_REQ = 9, > }; > > -/* Header fields */ > -#define RISCV_IOMMU_PREQ_HDR_PID GENMASK_ULL(31, 12) > -#define RISCV_IOMMU_PREQ_HDR_PV BIT_ULL(32) > -#define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33) > -#define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34) > -#define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40) > - > -/* Payload fields */ > -#define RISCV_IOMMU_PREQ_PAYLOAD_R BIT_ULL(0) > -#define RISCV_IOMMU_PREQ_PAYLOAD_W BIT_ULL(1) > -#define RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2) > -#define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0) > -#define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3) > -#define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12) > - > - > /* > * struct riscv_iommu_msi_pte - MSI Page Table Entry > */ > -- > 2.43.2 > > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h index 485f36b9c9..de599b80d6 100644 --- a/hw/riscv/riscv-iommu-bits.h +++ b/hw/riscv/riscv-iommu-bits.h @@ -50,8 +50,14 @@ struct riscv_iommu_pq_record { #define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33) #define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34) #define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40) + /* Payload fields */ +#define RISCV_IOMMU_PREQ_PAYLOAD_R BIT_ULL(0) +#define RISCV_IOMMU_PREQ_PAYLOAD_W BIT_ULL(1) +#define RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2) #define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0) +#define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3) +#define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12) /* Common field positions */ #define RISCV_IOMMU_PPN_FIELD GENMASK_ULL(53, 10) @@ -382,22 +388,6 @@ enum riscv_iommu_fq_ttypes { RISCV_IOMMU_FW_TTYPE_PCIE_MSG_REQ = 9, }; -/* Header fields */ -#define RISCV_IOMMU_PREQ_HDR_PID GENMASK_ULL(31, 12) -#define RISCV_IOMMU_PREQ_HDR_PV BIT_ULL(32) -#define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33) -#define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34) -#define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40) - -/* Payload fields */ -#define RISCV_IOMMU_PREQ_PAYLOAD_R BIT_ULL(0) -#define RISCV_IOMMU_PREQ_PAYLOAD_W BIT_ULL(1) -#define RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2) -#define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0) -#define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3) -#define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12) - - /* * struct riscv_iommu_msi_pte - MSI Page Table Entry */
Signed-off-by: Jason Chien <jason.chien@sifive.com> --- hw/riscv/riscv-iommu-bits.h | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-)