diff mbox series

[2/4] target/riscv: use RVB in RVA22U64

Message ID 20250114132012.1224941-3-dbarboza@ventanamicro.com (mailing list archive)
State New
Headers show
Series target/riscv: RVA23 profile support | expand

Commit Message

Daniel Henrique Barboza Jan. 14, 2025, 1:20 p.m. UTC 
From the time we added RVA22U64 until now the spec didn't declare 'RVB'
as a dependency, using zba/zbb/zbs instead. Since then the RVA22 spec
[1] added the following in the 'RVA22U64 Mandatory Extensions' section:

"B Bit-manipulation instructions

Note: The B extension comprises the Zba, Zbb, and Zbs extensions. At the
time of RVA22U64's ratification, the B extension had not yet been
defined, and so RVA22U64 explicitly mandated Zba, Zbb, and Zbs instead.
Mandating B is equivalent."

It is also equivalent to QEMU (see riscv_cpu_validate_b() in
target/riscv/tcg/tcg-cpu.c).

Finally, RVA23U64 [2] directly mentions RVB as a mandatory extension,
not citing zba/zbb/zbs.

To make it clear that RVA23U64 will extend RVA22U64 (i.e. RVA22 is a
parent of RVA23), use RVB in RVA22U64 as well. As a bonus we can also
exclude zba/zbb/zbs from 'ext_offsets' and make it a bit shorter.

(bios-tables-test change: zba/zbb/zbs no longer on riscv,isa)

[1] https://github.com/riscv/riscv-profiles/blob/main/src/profiles.adoc#61-rva22u64-profile
[2] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23u64-profile

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c                |   5 ++---
 tests/data/acpi/riscv64/virt/RHCT | Bin 398 -> 400 bytes
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT
index b14ec15e553200760a63aad65586913d31ea2edc..13c8025b868051485be5ba62974a22971a07bc6a 100644
GIT binary patch
delta 53
zcmeBUp1{l%<l!7LfsuiM@#{n`13^7TMg~>JqB1j+%-qDZl;ot1UQ&#clNpsc(ij;S
I3K$s}0ARKZK>z>%

delta 52
zcmbQh+{ern<l!9B$H>6Im@tvcKtP9)kwJyAsLaeHGdD3UC3&N_6yxMHMkS6EMh1pF
HMg|4|IwT82

Comments

Andrew Jones Jan. 14, 2025, 2:52 p.m. UTC | #1 
On Tue, Jan 14, 2025 at 10:20:10AM -0300, Daniel Henrique Barboza wrote:
> From the time we added RVA22U64 until now the spec didn't declare 'RVB'
> as a dependency, using zba/zbb/zbs instead. Since then the RVA22 spec
> [1] added the following in the 'RVA22U64 Mandatory Extensions' section:
> 
> "B Bit-manipulation instructions
> 
> Note: The B extension comprises the Zba, Zbb, and Zbs extensions. At the
> time of RVA22U64's ratification, the B extension had not yet been
> defined, and so RVA22U64 explicitly mandated Zba, Zbb, and Zbs instead.
> Mandating B is equivalent."
> 
> It is also equivalent to QEMU (see riscv_cpu_validate_b() in
> target/riscv/tcg/tcg-cpu.c).
> 
> Finally, RVA23U64 [2] directly mentions RVB as a mandatory extension,
> not citing zba/zbb/zbs.
> 
> To make it clear that RVA23U64 will extend RVA22U64 (i.e. RVA22 is a
> parent of RVA23), use RVB in RVA22U64 as well. As a bonus we can also
> exclude zba/zbb/zbs from 'ext_offsets' and make it a bit shorter.
> 
> (bios-tables-test change: zba/zbb/zbs no longer on riscv,isa)

We should still have zba/zbb/zbs on the ISA string. I don't think
Linux yet supports expanding a 'B' bundle into them and other SW
may also have not really cared about 'B' being designed to represent
preexisting extensions after having already learned how to detect
those extensions.

Anyway, what keeps them from being added? I don't see QEMU code
for that. I do expect a bios tables change though, since the ISA
string should now have 'B' added to it.

Thanks,
drew

> 
> [1] https://github.com/riscv/riscv-profiles/blob/main/src/profiles.adoc#61-rva22u64-profile
> [2] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23u64-profile
> 
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
>  target/riscv/cpu.c                |   5 ++---
>  tests/data/acpi/riscv64/virt/RHCT | Bin 398 -> 400 bytes
>  2 files changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b187ef2e4b..8d0563527f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2351,13 +2351,12 @@ static const PropertyInfo prop_marchid = {
>  static RISCVCPUProfile RVA22U64 = {
>      .parent = NULL,
>      .name = "rva22u64",
> -    .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU,
> +    .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU,
>      .priv_spec = RISCV_PROFILE_ATTR_UNUSED,
>      .satp_mode = RISCV_PROFILE_ATTR_UNUSED,
>      .ext_offsets = {
>          CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause),
> -        CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),
> -        CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin),
> +        CPU_CFG_OFFSET(ext_zfhmin),
>          CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr),
>          CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom),
>          CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz),
> diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT
> index b14ec15e553200760a63aad65586913d31ea2edc..13c8025b868051485be5ba62974a22971a07bc6a 100644
> GIT binary patch
> delta 53
> zcmeBUp1{l%<l!7LfsuiM@#{n`13^7TMg~>JqB1j+%-qDZl;ot1UQ&#clNpsc(ij;S
> I3K$s}0ARKZK>z>%
> 
> delta 52
> zcmbQh+{ern<l!9B$H>6Im@tvcKtP9)kwJyAsLaeHGdD3UC3&N_6yxMHMkS6EMh1pF
> HMg|4|IwT82
> 
> -- 
> 2.47.1
> 
>
Daniel Henrique Barboza Jan. 14, 2025, 4:08 p.m. UTC | #2 
On 1/14/25 11:52 AM, Andrew Jones wrote:
> On Tue, Jan 14, 2025 at 10:20:10AM -0300, Daniel Henrique Barboza wrote:
>>  From the time we added RVA22U64 until now the spec didn't declare 'RVB'
>> as a dependency, using zba/zbb/zbs instead. Since then the RVA22 spec
>> [1] added the following in the 'RVA22U64 Mandatory Extensions' section:
>>
>> "B Bit-manipulation instructions
>>
>> Note: The B extension comprises the Zba, Zbb, and Zbs extensions. At the
>> time of RVA22U64's ratification, the B extension had not yet been
>> defined, and so RVA22U64 explicitly mandated Zba, Zbb, and Zbs instead.
>> Mandating B is equivalent."
>>
>> It is also equivalent to QEMU (see riscv_cpu_validate_b() in
>> target/riscv/tcg/tcg-cpu.c).
>>
>> Finally, RVA23U64 [2] directly mentions RVB as a mandatory extension,
>> not citing zba/zbb/zbs.
>>
>> To make it clear that RVA23U64 will extend RVA22U64 (i.e. RVA22 is a
>> parent of RVA23), use RVB in RVA22U64 as well. As a bonus we can also
>> exclude zba/zbb/zbs from 'ext_offsets' and make it a bit shorter.
>>
>> (bios-tables-test change: zba/zbb/zbs no longer on riscv,isa)
> 
> We should still have zba/zbb/zbs on the ISA string. I don't think
> Linux yet supports expanding a 'B' bundle into them and other SW
> may also have not really cared about 'B' being designed to represent
> preexisting extensions after having already learned how to detect
> those extensions.

This has to do with how bios-tables-test works. The test doesn't boot the CPU
up to realize() and finalize() and, with this change, we ended up removing
zba/zbb/zbs from it because we won't reach riscv_cpu_validate_b() to add
them back.

I guess that in the end, aside from having a smaller ext list, there's not
much to gain from removing zba/zbb/zbs from the profile definition. We
can just add RVB and keep them.


Thanks,

Daniel

> 
> Anyway, what keeps them from being added? I don't see QEMU code
> for that. I do expect a bios tables change though, since the ISA
> string should now have 'B' added to it.
> 
> Thanks,
> drew
> 
>>
>> [1] https://github.com/riscv/riscv-profiles/blob/main/src/profiles.adoc#61-rva22u64-profile
>> [2] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23u64-profile
>>
>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> ---
>>   target/riscv/cpu.c                |   5 ++---
>>   tests/data/acpi/riscv64/virt/RHCT | Bin 398 -> 400 bytes
>>   2 files changed, 2 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index b187ef2e4b..8d0563527f 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -2351,13 +2351,12 @@ static const PropertyInfo prop_marchid = {
>>   static RISCVCPUProfile RVA22U64 = {
>>       .parent = NULL,
>>       .name = "rva22u64",
>> -    .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU,
>> +    .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU,
>>       .priv_spec = RISCV_PROFILE_ATTR_UNUSED,
>>       .satp_mode = RISCV_PROFILE_ATTR_UNUSED,
>>       .ext_offsets = {
>>           CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause),
>> -        CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),
>> -        CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin),
>> +        CPU_CFG_OFFSET(ext_zfhmin),
>>           CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr),
>>           CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom),
>>           CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz),
>> diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT
>> index b14ec15e553200760a63aad65586913d31ea2edc..13c8025b868051485be5ba62974a22971a07bc6a 100644
>> GIT binary patch
>> delta 53
>> zcmeBUp1{l%<l!7LfsuiM@#{n`13^7TMg~>JqB1j+%-qDZl;ot1UQ&#clNpsc(ij;S
>> I3K$s}0ARKZK>z>%
>>
>> delta 52
>> zcmbQh+{ern<l!9B$H>6Im@tvcKtP9)kwJyAsLaeHGdD3UC3&N_6yxMHMkS6EMh1pF
>> HMg|4|IwT82
>>
>> -- 
>> 2.47.1
>>
>>
Andrew Jones Jan. 14, 2025, 4:21 p.m. UTC | #3 
On Tue, Jan 14, 2025 at 01:08:46PM -0300, Daniel Henrique Barboza wrote:
> 
> 
> On 1/14/25 11:52 AM, Andrew Jones wrote:
> > On Tue, Jan 14, 2025 at 10:20:10AM -0300, Daniel Henrique Barboza wrote:
> > >  From the time we added RVA22U64 until now the spec didn't declare 'RVB'
> > > as a dependency, using zba/zbb/zbs instead. Since then the RVA22 spec
> > > [1] added the following in the 'RVA22U64 Mandatory Extensions' section:
> > > 
> > > "B Bit-manipulation instructions
> > > 
> > > Note: The B extension comprises the Zba, Zbb, and Zbs extensions. At the
> > > time of RVA22U64's ratification, the B extension had not yet been
> > > defined, and so RVA22U64 explicitly mandated Zba, Zbb, and Zbs instead.
> > > Mandating B is equivalent."
> > > 
> > > It is also equivalent to QEMU (see riscv_cpu_validate_b() in
> > > target/riscv/tcg/tcg-cpu.c).
> > > 
> > > Finally, RVA23U64 [2] directly mentions RVB as a mandatory extension,
> > > not citing zba/zbb/zbs.
> > > 
> > > To make it clear that RVA23U64 will extend RVA22U64 (i.e. RVA22 is a
> > > parent of RVA23), use RVB in RVA22U64 as well. As a bonus we can also
> > > exclude zba/zbb/zbs from 'ext_offsets' and make it a bit shorter.
> > > 
> > > (bios-tables-test change: zba/zbb/zbs no longer on riscv,isa)
> > 
> > We should still have zba/zbb/zbs on the ISA string. I don't think
> > Linux yet supports expanding a 'B' bundle into them and other SW
> > may also have not really cared about 'B' being designed to represent
> > preexisting extensions after having already learned how to detect
> > those extensions.
> 
> This has to do with how bios-tables-test works. The test doesn't boot the CPU
> up to realize() and finalize() and, with this change, we ended up removing
> zba/zbb/zbs from it because we won't reach riscv_cpu_validate_b() to add
> them back.

If we can't do a riscv_cpu_finalize_features() (and/or whatever else we
need to do) to ensure we have a complete ISA string, then I think we
should modify the test to somehow never check the ISA string entry of
the RHCT table.

> 
> I guess that in the end, aside from having a smaller ext list, there's not
> much to gain from removing zba/zbb/zbs from the profile definition. We
> can just add RVB and keep them.

While it doesn't really matter if we add them or not, I still think
the test should be modified such that we don't have to try to out-smart
it with profile and cpu definitions. Getting it to work would be best,
but getting it to ignore is also good since we wouldn't need to bother
modifying it every time we touch a cpu config.

Thanks,
drew

> 
> 
> Thanks,
> 
> Daniel
> 
> > 
> > Anyway, what keeps them from being added? I don't see QEMU code
> > for that. I do expect a bios tables change though, since the ISA
> > string should now have 'B' added to it.
> > 
> > Thanks,
> > drew
> > 
> > > 
> > > [1] https://github.com/riscv/riscv-profiles/blob/main/src/profiles.adoc#61-rva22u64-profile
> > > [2] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23u64-profile
> > > 
> > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> > > ---
> > >   target/riscv/cpu.c                |   5 ++---
> > >   tests/data/acpi/riscv64/virt/RHCT | Bin 398 -> 400 bytes
> > >   2 files changed, 2 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > index b187ef2e4b..8d0563527f 100644
> > > --- a/target/riscv/cpu.c
> > > +++ b/target/riscv/cpu.c
> > > @@ -2351,13 +2351,12 @@ static const PropertyInfo prop_marchid = {
> > >   static RISCVCPUProfile RVA22U64 = {
> > >       .parent = NULL,
> > >       .name = "rva22u64",
> > > -    .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU,
> > > +    .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU,
> > >       .priv_spec = RISCV_PROFILE_ATTR_UNUSED,
> > >       .satp_mode = RISCV_PROFILE_ATTR_UNUSED,
> > >       .ext_offsets = {
> > >           CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause),
> > > -        CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),
> > > -        CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin),
> > > +        CPU_CFG_OFFSET(ext_zfhmin),
> > >           CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr),
> > >           CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom),
> > >           CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz),
> > > diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT
> > > index b14ec15e553200760a63aad65586913d31ea2edc..13c8025b868051485be5ba62974a22971a07bc6a 100644
> > > GIT binary patch
> > > delta 53
> > > zcmeBUp1{l%<l!7LfsuiM@#{n`13^7TMg~>JqB1j+%-qDZl;ot1UQ&#clNpsc(ij;S
> > > I3K$s}0ARKZK>z>%
> > > 
> > > delta 52
> > > zcmbQh+{ern<l!9B$H>6Im@tvcKtP9)kwJyAsLaeHGdD3UC3&N_6yxMHMkS6EMh1pF
> > > HMg|4|IwT82
> > > 
> > > -- 
> > > 2.47.1
> > > 
> > > 
>
Daniel Henrique Barboza Jan. 14, 2025, 5:10 p.m. UTC | #4 
On 1/14/25 1:21 PM, Andrew Jones wrote:
> On Tue, Jan 14, 2025 at 01:08:46PM -0300, Daniel Henrique Barboza wrote:
>>
>>
>> On 1/14/25 11:52 AM, Andrew Jones wrote:
>>> On Tue, Jan 14, 2025 at 10:20:10AM -0300, Daniel Henrique Barboza wrote:
>>>>   From the time we added RVA22U64 until now the spec didn't declare 'RVB'
>>>> as a dependency, using zba/zbb/zbs instead. Since then the RVA22 spec
>>>> [1] added the following in the 'RVA22U64 Mandatory Extensions' section:
>>>>
>>>> "B Bit-manipulation instructions
>>>>
>>>> Note: The B extension comprises the Zba, Zbb, and Zbs extensions. At the
>>>> time of RVA22U64's ratification, the B extension had not yet been
>>>> defined, and so RVA22U64 explicitly mandated Zba, Zbb, and Zbs instead.
>>>> Mandating B is equivalent."
>>>>
>>>> It is also equivalent to QEMU (see riscv_cpu_validate_b() in
>>>> target/riscv/tcg/tcg-cpu.c).
>>>>
>>>> Finally, RVA23U64 [2] directly mentions RVB as a mandatory extension,
>>>> not citing zba/zbb/zbs.
>>>>
>>>> To make it clear that RVA23U64 will extend RVA22U64 (i.e. RVA22 is a
>>>> parent of RVA23), use RVB in RVA22U64 as well. As a bonus we can also
>>>> exclude zba/zbb/zbs from 'ext_offsets' and make it a bit shorter.
>>>>
>>>> (bios-tables-test change: zba/zbb/zbs no longer on riscv,isa)
>>>
>>> We should still have zba/zbb/zbs on the ISA string. I don't think
>>> Linux yet supports expanding a 'B' bundle into them and other SW
>>> may also have not really cared about 'B' being designed to represent
>>> preexisting extensions after having already learned how to detect
>>> those extensions.
>>
>> This has to do with how bios-tables-test works. The test doesn't boot the CPU
>> up to realize() and finalize() and, with this change, we ended up removing
>> zba/zbb/zbs from it because we won't reach riscv_cpu_validate_b() to add
>> them back.
> 
> If we can't do a riscv_cpu_finalize_features() (and/or whatever else we
> need to do) to ensure we have a complete ISA string, then I think we
> should modify the test to somehow never check the ISA string entry of
> the RHCT table.
> 
>>
>> I guess that in the end, aside from having a smaller ext list, there's not
>> much to gain from removing zba/zbb/zbs from the profile definition. We
>> can just add RVB and keep them.
> 
> While it doesn't really matter if we add them or not, I still think
> the test should be modified such that we don't have to try to out-smart
> it with profile and cpu definitions. Getting it to work would be best,
> but getting it to ignore is also good since we wouldn't need to bother
> modifying it every time we touch a cpu config.

In theory the test is using rva22 cpus on purpose to try to minimize this
kind of thing. Back then we were worried that the changes in rv64 CPU would
trigger too much test changes. In practice every time we add some new
riscv,isa DT entry, due to an innate QEMU feature that we're now advertising
and whatnot, this test will break.

One thing that crossed my mind but I didn't get to implement it is to provide
a static riscv,isa based on accelerator, e.g. if we're running '-accel qtest'
then we would always return the same riscv,isa regardless of the changes
made in the common emulation. I'm not sure the implications of doing that but
it's something that I think it's worth exploring. Otherwise we'll have to
keep updating this ACPI bios table test from time to time.


Thanks,

Daniel

> 
> Thanks,
> drew
> 
>>
>>
>> Thanks,
>>
>> Daniel
>>
>>>
>>> Anyway, what keeps them from being added? I don't see QEMU code
>>> for that. I do expect a bios tables change though, since the ISA
>>> string should now have 'B' added to it.
>>>
>>> Thanks,
>>> drew
>>>
>>>>
>>>> [1] https://github.com/riscv/riscv-profiles/blob/main/src/profiles.adoc#61-rva22u64-profile
>>>> [2] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23u64-profile
>>>>
>>>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>>>> ---
>>>>    target/riscv/cpu.c                |   5 ++---
>>>>    tests/data/acpi/riscv64/virt/RHCT | Bin 398 -> 400 bytes
>>>>    2 files changed, 2 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>>>> index b187ef2e4b..8d0563527f 100644
>>>> --- a/target/riscv/cpu.c
>>>> +++ b/target/riscv/cpu.c
>>>> @@ -2351,13 +2351,12 @@ static const PropertyInfo prop_marchid = {
>>>>    static RISCVCPUProfile RVA22U64 = {
>>>>        .parent = NULL,
>>>>        .name = "rva22u64",
>>>> -    .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU,
>>>> +    .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU,
>>>>        .priv_spec = RISCV_PROFILE_ATTR_UNUSED,
>>>>        .satp_mode = RISCV_PROFILE_ATTR_UNUSED,
>>>>        .ext_offsets = {
>>>>            CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause),
>>>> -        CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),
>>>> -        CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin),
>>>> +        CPU_CFG_OFFSET(ext_zfhmin),
>>>>            CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr),
>>>>            CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom),
>>>>            CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz),
>>>> diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT
>>>> index b14ec15e553200760a63aad65586913d31ea2edc..13c8025b868051485be5ba62974a22971a07bc6a 100644
>>>> GIT binary patch
>>>> delta 53
>>>> zcmeBUp1{l%<l!7LfsuiM@#{n`13^7TMg~>JqB1j+%-qDZl;ot1UQ&#clNpsc(ij;S
>>>> I3K$s}0ARKZK>z>%
>>>>
>>>> delta 52
>>>> zcmbQh+{ern<l!9B$H>6Im@tvcKtP9)kwJyAsLaeHGdD3UC3&N_6yxMHMkS6EMh1pF
>>>> HMg|4|IwT82
>>>>
>>>> -- 
>>>> 2.47.1
>>>>
>>>>
>>
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b187ef2e4b..8d0563527f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2351,13 +2351,12 @@  static const PropertyInfo prop_marchid = {
 static RISCVCPUProfile RVA22U64 = {
     .parent = NULL,
     .name = "rva22u64",
-    .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU,
+    .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU,
     .priv_spec = RISCV_PROFILE_ATTR_UNUSED,
     .satp_mode = RISCV_PROFILE_ATTR_UNUSED,
     .ext_offsets = {
         CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause),
-        CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),
-        CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin),
+        CPU_CFG_OFFSET(ext_zfhmin),
         CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr),
         CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom),
         CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz),