| Message ID | 20250115110142.3501140-1-quic_mmanikan@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: qcom: ipq9574: enable fast mode for i2c3 | expand |
On Wed, Jan 15, 2025 at 04:31:42PM +0530, Manikanta Mylavarapu wrote: > Configure the blsp1 i2c3 bus to operate at 400 kHz > for fast mode. This is usually a board property rather than an SoC one. > > Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> > --- > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > index 942290028972..b35df590a794 100644 > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > @@ -621,6 +621,7 @@ blsp1_i2c3: i2c@78b8000 { > clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, > <&gcc GCC_BLSP1_AHB_CLK>; > clock-names = "core", "iface"; > + clock-frequency = <400000>; > assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; > assigned-clock-rates = <50000000>; > dmas = <&blsp_dma 18>, <&blsp_dma 19>; > -- > 2.34.1 >
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 942290028972..b35df590a794 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -621,6 +621,7 @@ blsp1_i2c3: i2c@78b8000 { clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + clock-frequency = <400000>; assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; assigned-clock-rates = <50000000>; dmas = <&blsp_dma 18>, <&blsp_dma 19>;
Configure the blsp1 i2c3 bus to operate at 400 kHz for fast mode. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 1 + 1 file changed, 1 insertion(+)