| Message ID | 20250116-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v4-13-74749c6eba33@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/msm/dpu: Support quad pipe with dual-DSI | expand |
On Thu, Jan 16, 2025 at 03:26:02PM +0800, Jun Nie wrote: > The content of every half of screen is sent out via one interface in > dual-DSI case. The content for every interface is blended by a LM > pair in quad-pipe case, thus a LM pair should not blend any content > that cross the half of screen in this case. Clip plane into pipes per > left and right half screen ROI if topology is quad pipe case. > > The clipped rectangle on every half of screen will be split further > by half if its width still exceeds limit. futher handled by two pipes if its width exceeds a limit for a single pipe. > > Signed-off-by: Jun Nie <jun.nie@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 +++ > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 + > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 138 +++++++++++++++++++--------- > 4 files changed, 112 insertions(+), 41 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > index 5ae640da53fbf..a900220deeb35 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > @@ -1361,6 +1361,17 @@ int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) > return 0; > } > > +/** > + * dpu_crtc_get_num_lm - Get mixer number in this CRTC pipeline > + * @state: Pointer to drm crtc state object > + */ > +unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state) > +{ > + struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); > + > + return cstate->num_mixers; > +} > + > #ifdef CONFIG_DEBUG_FS > static int _dpu_debugfs_status_show(struct seq_file *s, void *data) > { > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h > index 0b148f3ce0d7a..b14bab2754635 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h > @@ -264,4 +264,6 @@ static inline enum dpu_crtc_client_type dpu_crtc_get_client_type( > > void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event); > > +unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state); > + > #endif /* _DPU_CRTC_H_ */ > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h > index 56a0edf2a57c6..39fe338e76691 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h > @@ -145,11 +145,13 @@ struct dpu_hw_pixel_ext { > * such as decimation, flip etc to program this field > * @dest_rect: destination ROI. > * @rotation: simplified drm rotation hint > + * @valid: notify that this pipe and config is in use > */ > struct dpu_sw_pipe_cfg { > struct drm_rect src_rect; > struct drm_rect dst_rect; > unsigned int rotation; > + bool valid; Commit message doesn't describe why this is necessary at all. Why isn't it enough to check pipe->sspp as the code has been doing up to this point? > }; > > /** > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > index 3795576e2eedd..4bcd7b1a05c16 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > @@ -831,8 +831,12 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane, > struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); > struct dpu_sw_pipe_cfg *pipe_cfg; > struct dpu_sw_pipe_cfg *r_pipe_cfg; > + struct dpu_sw_pipe_cfg init_pipe_cfg; > struct drm_rect fb_rect = { 0 }; > + const struct drm_display_mode *mode = &crtc_state->adjusted_mode; > uint32_t max_linewidth; > + u32 num_lm; > + int stage_id, num_stages; > > min_scale = FRAC_16_16(1, MAX_UPSCALE_RATIO); > max_scale = MAX_DOWNSCALE_RATIO << 16; > @@ -855,13 +859,10 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane, > return -EINVAL; > } > > - /* move the assignment here, to ease handling to another pairs later */ > - pipe_cfg = &pstate->pipe_cfg[0]; > - r_pipe_cfg = &pstate->pipe_cfg[1]; > - /* state->src is 16.16, src_rect is not */ > - drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); > + num_lm = dpu_crtc_get_num_lm(crtc_state); > > - pipe_cfg->dst_rect = new_plane_state->dst; > + /* state->src is 16.16, src_rect is not */ > + drm_rect_fp_to_int(&init_pipe_cfg.src_rect, &new_plane_state->src); > > fb_rect.x2 = new_plane_state->fb->width; > fb_rect.y2 = new_plane_state->fb->height; > @@ -886,35 +887,93 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane, > > max_linewidth = pdpu->catalog->caps->max_linewidth; > > - drm_rect_rotate(&pipe_cfg->src_rect, > + drm_rect_rotate(&init_pipe_cfg.src_rect, > new_plane_state->fb->width, new_plane_state->fb->height, > new_plane_state->rotation); > > - if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || > - _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) { > - if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { > - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", > - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); > - return -E2BIG; > + /* > + * We have 1 mixer pair cfg for 1:1:1 and 2:2:1 topology, 2 mixer pair > + * configs for left and right half screen in case of 4:4:2 topology. > + * But we may have 2 rect to split wide plane that exceeds limit with 1 > + * config for 2:2:1. So need to handle both wide plane splitting, and > + * plane on right half for quad-pipe case. Check dest rectangle only on the right side? > + * left/right clipping first, then check wide rectangle splitting in > + * every half next. > + */ > + num_stages = (num_lm + 1) / 2;
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> 于2025年1月16日周四 16:14写道： > > On Thu, Jan 16, 2025 at 03:26:02PM +0800, Jun Nie wrote: > > The content of every half of screen is sent out via one interface in > > dual-DSI case. The content for every interface is blended by a LM > > pair in quad-pipe case, thus a LM pair should not blend any content > > that cross the half of screen in this case. Clip plane into pipes per > > left and right half screen ROI if topology is quad pipe case. > > > > The clipped rectangle on every half of screen will be split further > > by half if its width still exceeds limit. > > futher handled by two pipes if its width exceeds a limit for a single > pipe. Accepted. > > > > > Signed-off-by: Jun Nie <jun.nie@linaro.org> > > --- > > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 +++ > > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 138 +++++++++++++++++++--------- > > 4 files changed, 112 insertions(+), 41 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > > index 5ae640da53fbf..a900220deeb35 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > > @@ -1361,6 +1361,17 @@ int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) > > return 0; > > } > > > > +/** > > + * dpu_crtc_get_num_lm - Get mixer number in this CRTC pipeline > > + * @state: Pointer to drm crtc state object > > + */ > > +unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state) > > +{ > > + struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); > > + > > + return cstate->num_mixers; > > +} > > + > > #ifdef CONFIG_DEBUG_FS > > static int _dpu_debugfs_status_show(struct seq_file *s, void *data) > > { > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h > > index 0b148f3ce0d7a..b14bab2754635 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h > > @@ -264,4 +264,6 @@ static inline enum dpu_crtc_client_type dpu_crtc_get_client_type( > > > > void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event); > > > > +unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state); > > + > > #endif /* _DPU_CRTC_H_ */ > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h > > index 56a0edf2a57c6..39fe338e76691 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h > > @@ -145,11 +145,13 @@ struct dpu_hw_pixel_ext { > > * such as decimation, flip etc to program this field > > * @dest_rect: destination ROI. > > * @rotation: simplified drm rotation hint > > + * @valid: notify that this pipe and config is in use > > */ > > struct dpu_sw_pipe_cfg { > > struct drm_rect src_rect; > > struct drm_rect dst_rect; > > unsigned int rotation; > > + bool valid; > > Commit message doesn't describe why this is necessary at all. Why isn't > it enough to check pipe->sspp as the code has been doing up to this > point? We test non-zero width of r_pipe or check pipe->sspp to decide whether to allocate SSPP and go thru the routine for the r_pipe when we have 2 pipes at most. With 4 pipes, it is a bit complex to handle it this way because the 2rd and the 4th pipes may be not valid when splitting the plane. A valid flag is more straightforward for later handling. > > > }; > > > > /** > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > > index 3795576e2eedd..4bcd7b1a05c16 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > > @@ -831,8 +831,12 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane, > > struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); > > struct dpu_sw_pipe_cfg *pipe_cfg; > > struct dpu_sw_pipe_cfg *r_pipe_cfg; > > + struct dpu_sw_pipe_cfg init_pipe_cfg; > > struct drm_rect fb_rect = { 0 }; > > + const struct drm_display_mode *mode = &crtc_state->adjusted_mode; > > uint32_t max_linewidth; > > + u32 num_lm; > > + int stage_id, num_stages; > > > > min_scale = FRAC_16_16(1, MAX_UPSCALE_RATIO); > > max_scale = MAX_DOWNSCALE_RATIO << 16; > > @@ -855,13 +859,10 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane, > > return -EINVAL; > > } > > > > - /* move the assignment here, to ease handling to another pairs later */ > > - pipe_cfg = &pstate->pipe_cfg[0]; > > - r_pipe_cfg = &pstate->pipe_cfg[1]; > > - /* state->src is 16.16, src_rect is not */ > > - drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); > > + num_lm = dpu_crtc_get_num_lm(crtc_state); > > > > - pipe_cfg->dst_rect = new_plane_state->dst; > > + /* state->src is 16.16, src_rect is not */ > > + drm_rect_fp_to_int(&init_pipe_cfg.src_rect, &new_plane_state->src); > > > > fb_rect.x2 = new_plane_state->fb->width; > > fb_rect.y2 = new_plane_state->fb->height; > > @@ -886,35 +887,93 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane, > > > > max_linewidth = pdpu->catalog->caps->max_linewidth; > > > > - drm_rect_rotate(&pipe_cfg->src_rect, > > + drm_rect_rotate(&init_pipe_cfg.src_rect, > > new_plane_state->fb->width, new_plane_state->fb->height, > > new_plane_state->rotation); > > > > - if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || > > - _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) { > > - if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { > > - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", > > - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); > > - return -E2BIG; > > + /* > > + * We have 1 mixer pair cfg for 1:1:1 and 2:2:1 topology, 2 mixer pair > > + * configs for left and right half screen in case of 4:4:2 topology. > > + * But we may have 2 rect to split wide plane that exceeds limit with 1 > > + * config for 2:2:1. So need to handle both wide plane splitting, and > > + * plane on right half for quad-pipe case. Check dest rectangle > > only on the right side? Yeah, below shall be better. So need to handle both wide plane splitting, and two halves of screen splitting for quad-pipe case. > > > + * left/right clipping first, then check wide rectangle splitting in > > + * every half next. > > + */ > > + num_stages = (num_lm + 1) / 2; > > -- > With best wishes > Dmitry
On Thu, Jan 16, 2025 at 06:20:48PM +0800, Jun Nie wrote: > Dmitry Baryshkov <dmitry.baryshkov@linaro.org> 于2025年1月16日周四 16:14写道： > > > > On Thu, Jan 16, 2025 at 03:26:02PM +0800, Jun Nie wrote: > > > The content of every half of screen is sent out via one interface in > > > dual-DSI case. The content for every interface is blended by a LM > > > pair in quad-pipe case, thus a LM pair should not blend any content > > > that cross the half of screen in this case. Clip plane into pipes per > > > left and right half screen ROI if topology is quad pipe case. > > > > > > The clipped rectangle on every half of screen will be split further > > > by half if its width still exceeds limit. > > > > futher handled by two pipes if its width exceeds a limit for a single > > pipe. > > Accepted. > > > > > > > > Signed-off-by: Jun Nie <jun.nie@linaro.org> > > > --- > > > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 +++ > > > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 + > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 + > > > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 138 +++++++++++++++++++--------- > > > 4 files changed, 112 insertions(+), 41 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > > > index 5ae640da53fbf..a900220deeb35 100644 > > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > > > @@ -1361,6 +1361,17 @@ int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) > > > return 0; > > > } > > > > > > +/** > > > + * dpu_crtc_get_num_lm - Get mixer number in this CRTC pipeline > > > + * @state: Pointer to drm crtc state object > > > + */ > > > +unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state) > > > +{ > > > + struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); > > > + > > > + return cstate->num_mixers; > > > +} > > > + > > > #ifdef CONFIG_DEBUG_FS > > > static int _dpu_debugfs_status_show(struct seq_file *s, void *data) > > > { > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h > > > index 0b148f3ce0d7a..b14bab2754635 100644 > > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h > > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h > > > @@ -264,4 +264,6 @@ static inline enum dpu_crtc_client_type dpu_crtc_get_client_type( > > > > > > void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event); > > > > > > +unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state); > > > + > > > #endif /* _DPU_CRTC_H_ */ > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h > > > index 56a0edf2a57c6..39fe338e76691 100644 > > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h > > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h > > > @@ -145,11 +145,13 @@ struct dpu_hw_pixel_ext { > > > * such as decimation, flip etc to program this field > > > * @dest_rect: destination ROI. > > > * @rotation: simplified drm rotation hint > > > + * @valid: notify that this pipe and config is in use > > > */ > > > struct dpu_sw_pipe_cfg { > > > struct drm_rect src_rect; > > > struct drm_rect dst_rect; > > > unsigned int rotation; > > > + bool valid; > > > > Commit message doesn't describe why this is necessary at all. Why isn't > > it enough to check pipe->sspp as the code has been doing up to this > > point? > > We test non-zero width of r_pipe or check pipe->sspp to decide whether > to allocate SSPP and go thru the routine for the r_pipe when we have 2 > pipes at most. With 4 pipes, it is a bit complex to handle it this way because > the 2rd and the 4th pipes may be not valid when splitting the plane. A valid > flag is more straightforward for later handling. Why? Even for 4-pipe case we need to allocate SSPP rect if drm_rect_width is non-0, that's for the atomic_check() function. And later we should be using pipe->sspp to check if it is valid or not. Adding extra flag complicates code because it can easily become unsync with the rest of the pipe configuration. > > > > > > }; > > > > > > /** > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > > > index 3795576e2eedd..4bcd7b1a05c16 100644 > > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > > > @@ -831,8 +831,12 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane, > > > struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); > > > struct dpu_sw_pipe_cfg *pipe_cfg; > > > struct dpu_sw_pipe_cfg *r_pipe_cfg; > > > + struct dpu_sw_pipe_cfg init_pipe_cfg; > > > struct drm_rect fb_rect = { 0 }; > > > + const struct drm_display_mode *mode = &crtc_state->adjusted_mode; > > > uint32_t max_linewidth; > > > + u32 num_lm; > > > + int stage_id, num_stages; > > > > > > min_scale = FRAC_16_16(1, MAX_UPSCALE_RATIO); > > > max_scale = MAX_DOWNSCALE_RATIO << 16; > > > @@ -855,13 +859,10 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane, > > > return -EINVAL; > > > } > > > > > > - /* move the assignment here, to ease handling to another pairs later */ > > > - pipe_cfg = &pstate->pipe_cfg[0]; > > > - r_pipe_cfg = &pstate->pipe_cfg[1]; > > > - /* state->src is 16.16, src_rect is not */ > > > - drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); > > > + num_lm = dpu_crtc_get_num_lm(crtc_state); > > > > > > - pipe_cfg->dst_rect = new_plane_state->dst; > > > + /* state->src is 16.16, src_rect is not */ > > > + drm_rect_fp_to_int(&init_pipe_cfg.src_rect, &new_plane_state->src); > > > > > > fb_rect.x2 = new_plane_state->fb->width; > > > fb_rect.y2 = new_plane_state->fb->height; > > > @@ -886,35 +887,93 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane, > > > > > > max_linewidth = pdpu->catalog->caps->max_linewidth; > > > > > > - drm_rect_rotate(&pipe_cfg->src_rect, > > > + drm_rect_rotate(&init_pipe_cfg.src_rect, > > > new_plane_state->fb->width, new_plane_state->fb->height, > > > new_plane_state->rotation); > > > > > > - if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || > > > - _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) { > > > - if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { > > > - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", > > > - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); > > > - return -E2BIG; > > > + /* > > > + * We have 1 mixer pair cfg for 1:1:1 and 2:2:1 topology, 2 mixer pair > > > + * configs for left and right half screen in case of 4:4:2 topology. > > > + * But we may have 2 rect to split wide plane that exceeds limit with 1 > > > + * config for 2:2:1. So need to handle both wide plane splitting, and > > > + * plane on right half for quad-pipe case. Check dest rectangle > > > > only on the right side? > > Yeah, below shall be better. > So need to handle both wide plane splitting, and two halves of screen splitting > for quad-pipe case. > > > > > + * left/right clipping first, then check wide rectangle splitting in > > > + * every half next. > > > + */ > > > + num_stages = (num_lm + 1) / 2; > > > > -- > > With best wishes > > Dmitry
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 5ae640da53fbf..a900220deeb35 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1361,6 +1361,17 @@ int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) return 0; } +/** + * dpu_crtc_get_num_lm - Get mixer number in this CRTC pipeline + * @state: Pointer to drm crtc state object + */ +unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state) +{ + struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); + + return cstate->num_mixers; +} + #ifdef CONFIG_DEBUG_FS static int _dpu_debugfs_status_show(struct seq_file *s, void *data) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h index 0b148f3ce0d7a..b14bab2754635 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -264,4 +264,6 @@ static inline enum dpu_crtc_client_type dpu_crtc_get_client_type( void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event); +unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state); + #endif /* _DPU_CRTC_H_ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 56a0edf2a57c6..39fe338e76691 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -145,11 +145,13 @@ struct dpu_hw_pixel_ext { * such as decimation, flip etc to program this field * @dest_rect: destination ROI. * @rotation: simplified drm rotation hint + * @valid: notify that this pipe and config is in use */ struct dpu_sw_pipe_cfg { struct drm_rect src_rect; struct drm_rect dst_rect; unsigned int rotation; + bool valid; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 3795576e2eedd..4bcd7b1a05c16 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -831,8 +831,12 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane, struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); struct dpu_sw_pipe_cfg *pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg; + struct dpu_sw_pipe_cfg init_pipe_cfg; struct drm_rect fb_rect = { 0 }; + const struct drm_display_mode *mode = &crtc_state->adjusted_mode; uint32_t max_linewidth; + u32 num_lm; + int stage_id, num_stages; min_scale = FRAC_16_16(1, MAX_UPSCALE_RATIO); max_scale = MAX_DOWNSCALE_RATIO << 16; @@ -855,13 +859,10 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane, return -EINVAL; } - /* move the assignment here, to ease handling to another pairs later */ - pipe_cfg = &pstate->pipe_cfg[0]; - r_pipe_cfg = &pstate->pipe_cfg[1]; - /* state->src is 16.16, src_rect is not */ - drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); + num_lm = dpu_crtc_get_num_lm(crtc_state); - pipe_cfg->dst_rect = new_plane_state->dst; + /* state->src is 16.16, src_rect is not */ + drm_rect_fp_to_int(&init_pipe_cfg.src_rect, &new_plane_state->src); fb_rect.x2 = new_plane_state->fb->width; fb_rect.y2 = new_plane_state->fb->height; @@ -886,35 +887,93 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane, max_linewidth = pdpu->catalog->caps->max_linewidth; - drm_rect_rotate(&pipe_cfg->src_rect, + drm_rect_rotate(&init_pipe_cfg.src_rect, new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); - if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || - _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) { - if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); - return -E2BIG; + /* + * We have 1 mixer pair cfg for 1:1:1 and 2:2:1 topology, 2 mixer pair + * configs for left and right half screen in case of 4:4:2 topology. + * But we may have 2 rect to split wide plane that exceeds limit with 1 + * config for 2:2:1. So need to handle both wide plane splitting, and + * plane on right half for quad-pipe case. Check dest rectangle + * left/right clipping first, then check wide rectangle splitting in + * every half next. + */ + num_stages = (num_lm + 1) / 2; + /* iterate mixer configs for this plane, to separate left/right with the id */ + for (stage_id = 0; stage_id < num_stages; stage_id++) { + struct drm_rect mixer_rect = {stage_id * mode->hdisplay / num_stages, 0, + (stage_id + 1) * mode->hdisplay / num_stages, + mode->vdisplay}; + int cfg_idx = stage_id * PIPES_PER_STAGE; + + pipe_cfg = &pstate->pipe_cfg[cfg_idx]; + r_pipe_cfg = &pstate->pipe_cfg[cfg_idx + 1]; + + drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); + pipe_cfg->dst_rect = new_plane_state->dst; + + DPU_DEBUG_PLANE(pdpu, "checking src " DRM_RECT_FMT + " vs clip window " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), + DRM_RECT_ARG(&mixer_rect)); + + /* + * If this plane does not fall into mixer rect, check next + * mixer rect. + */ + if (!drm_rect_clip_scaled(&pipe_cfg->src_rect, + &pipe_cfg->dst_rect, + &mixer_rect)) { + pipe_cfg->valid = false; + r_pipe_cfg->valid = false; + continue; } - *r_pipe_cfg = *pipe_cfg; - pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; - pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; - r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; - r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; - } else { - memset(r_pipe_cfg, 0, sizeof(*r_pipe_cfg)); - } + pipe_cfg->valid = true; + pipe_cfg->dst_rect.x1 -= mixer_rect.x1; + pipe_cfg->dst_rect.x2 -= mixer_rect.x1; + + DPU_DEBUG_PLANE(pdpu, "Got clip src:" DRM_RECT_FMT " dst: " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), DRM_RECT_ARG(&pipe_cfg->dst_rect)); + + /* Split wide rect into 2 rect */ + if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || + _dpu_plane_calc_clk(mode, pipe_cfg) > max_mdp_clk_rate) { + + if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; + } + + memcpy(r_pipe_cfg, pipe_cfg, sizeof(struct dpu_sw_pipe_cfg)); + pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; + pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; + r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; + r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; + r_pipe_cfg->valid = true; + DPU_DEBUG_PLANE(pdpu, "Split wide plane into:" + DRM_RECT_FMT " and " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), + DRM_RECT_ARG(&r_pipe_cfg->src_rect)); + } else { + r_pipe_cfg->valid = false; + } - drm_rect_rotate_inv(&pipe_cfg->src_rect, - new_plane_state->fb->width, new_plane_state->fb->height, - new_plane_state->rotation); - if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) - drm_rect_rotate_inv(&r_pipe_cfg->src_rect, - new_plane_state->fb->width, new_plane_state->fb->height, + drm_rect_rotate_inv(&pipe_cfg->src_rect, + new_plane_state->fb->width, + new_plane_state->fb->height, new_plane_state->rotation); + if (r_pipe_cfg->valid) + drm_rect_rotate_inv(&r_pipe_cfg->src_rect, + new_plane_state->fb->width, + new_plane_state->fb->height, + new_plane_state->rotation); + } + pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); return 0; @@ -954,20 +1013,17 @@ static int dpu_plane_atomic_check_sspp(struct drm_plane *plane, drm_atomic_get_new_plane_state(state, plane); struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe *pipe = &pstate->pipe[0]; - struct dpu_sw_pipe *r_pipe = &pstate->pipe[1]; - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0]; - struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1]; - int ret = 0; - - ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, - &crtc_state->adjusted_mode, - new_plane_state); - if (ret) - return ret; + struct dpu_sw_pipe *pipe; + struct dpu_sw_pipe_cfg *pipe_cfg; + int ret = 0, i; - if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) { - ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, + for (i = 0; i < PIPES_PER_PLANE; i++) { + pipe = &pstate->pipe[i]; + pipe_cfg = &pstate->pipe_cfg[i]; + if (!pipe_cfg->valid || !pipe->sspp) + continue; + DPU_DEBUG_PLANE(pdpu, "pipe %d is in use, validate it\n", i); + ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, &crtc_state->adjusted_mode, new_plane_state); if (ret) @@ -990,7 +1046,7 @@ static bool dpu_plane_try_multirect_parallel(struct dpu_sw_pipe *pipe, struct dp r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; - if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) { + if (r_pipe_cfg->valid && drm_rect_width(&r_pipe_cfg->src_rect) != 0) { if (!dpu_plane_is_multirect_parallel_capable(pipe->sspp, pipe_cfg, fmt, max_linewidth) || !dpu_plane_is_multirect_parallel_capable(pipe->sspp, r_pipe_cfg, fmt, max_linewidth)) return false;
The content of every half of screen is sent out via one interface in dual-DSI case. The content for every interface is blended by a LM pair in quad-pipe case, thus a LM pair should not blend any content that cross the half of screen in this case. Clip plane into pipes per left and right half screen ROI if topology is quad pipe case. The clipped rectangle on every half of screen will be split further by half if its width still exceeds limit. Signed-off-by: Jun Nie <jun.nie@linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 138 +++++++++++++++++++--------- 4 files changed, 112 insertions(+), 41 deletions(-)