| Message ID | 20250116131539.2475785-1-cleger@rivosinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v9] target/riscv: Add Smdbltrp ISA extension enable switch | expand |
On 1/16/25 10:15 AM, Clément Léger wrote: > Add the switch to enable the Smdbltrp ISA extension and disable it for > the max cpu. Indeed, OpenSBI when Smdbltrp is present, M-mode double > trap is enabled by default and MSTATUS.MDT needs to be cleared to avoid > taking a double trap. OpenSBI does not currently support it so disable > it for the max cpu to avoid breaking regression tests. > > Signed-off-by: Clément Léger <cleger@rivosinc.com> > --- Tested by removing: drop 0b443cba0d target/riscv: Add Smdbltrp ISA extension enable switch From riscv-to-apply.next, applying this patch in its place. 'make check-functional' is working again, i.e. there's no problems in booting the 'max' CPU. Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Note: this is a resend of patch 9/9 from the double trap series which > disables this extension for the max cpu. It can be cherry-picked as a > direct replacement of previous commit. > > target/riscv/cpu.c | 2 ++ > target/riscv/tcg/tcg-cpu.c | 10 ++++++++++ > 2 files changed, 12 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index e3ed11b0fd..bddf1ba75e 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -194,6 +194,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_13_0, ext_smcdeleg), > ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_13_0, ext_smcsrind), > + ISA_EXT_DATA_ENTRY(smdbltrp, PRIV_VERSION_1_13_0, ext_smdbltrp), > ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), > ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), > ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm), > @@ -1626,6 +1627,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false), > > MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), > + MULTI_EXT_CFG_BOOL("smdbltrp", ext_smdbltrp, false), > MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), > MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), > MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false), > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 48be24bbbe..0a137281de 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -1439,6 +1439,16 @@ static void riscv_init_max_cpu_extensions(Object *obj) > isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); > qemu_log("Smrnmi is disabled in the 'max' type CPU\n"); > } > + > + /* > + * ext_smdbltrp requires the firmware to clear MSTATUS.MDT on startup to > + * avoid generating a double trap. OpenSBI does not currently support it, > + * disable it for now. > + */ > + if (cpu->cfg.ext_smdbltrp) { > + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smdbltrp), false); > + qemu_log("Smdbltrp is disabled in the 'max' type CPU\n"); > + } > } > > static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e3ed11b0fd..bddf1ba75e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -194,6 +194,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_13_0, ext_smcdeleg), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_13_0, ext_smcsrind), + ISA_EXT_DATA_ENTRY(smdbltrp, PRIV_VERSION_1_13_0, ext_smdbltrp), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm), @@ -1626,6 +1627,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false), MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), + MULTI_EXT_CFG_BOOL("smdbltrp", ext_smdbltrp, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 48be24bbbe..0a137281de 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1439,6 +1439,16 @@ static void riscv_init_max_cpu_extensions(Object *obj) isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); qemu_log("Smrnmi is disabled in the 'max' type CPU\n"); } + + /* + * ext_smdbltrp requires the firmware to clear MSTATUS.MDT on startup to + * avoid generating a double trap. OpenSBI does not currently support it, + * disable it for now. + */ + if (cpu->cfg.ext_smdbltrp) { + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smdbltrp), false); + qemu_log("Smdbltrp is disabled in the 'max' type CPU\n"); + } } static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
Add the switch to enable the Smdbltrp ISA extension and disable it for the max cpu. Indeed, OpenSBI when Smdbltrp is present, M-mode double trap is enabled by default and MSTATUS.MDT needs to be cleared to avoid taking a double trap. OpenSBI does not currently support it so disable it for the max cpu to avoid breaking regression tests. Signed-off-by: Clément Léger <cleger@rivosinc.com> --- Note: this is a resend of patch 9/9 from the double trap series which disables this extension for the max cpu. It can be cherry-picked as a direct replacement of previous commit. target/riscv/cpu.c | 2 ++ target/riscv/tcg/tcg-cpu.c | 10 ++++++++++ 2 files changed, 12 insertions(+)