| Message ID | 20250113-sm8750_crypto_master-v1-2-d8e265729848@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Delegated to: | Herbert Xu |
| Headers | show |
| Series | arm64: dts: qcom: sm8750: Introduce crypto support for SM8750 | expand |
On Mon, Jan 13, 2025 at 01:16:22PM -0800, Melody Olvera wrote: > From: Gaurav Kashyap <quic_gaurkash@quicinc.com> > > Add the QCE and Crypto BAM DMA nodes. > > Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com> > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sm8750.dtsi | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi > index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..1ddb33ea83885e73bf15244c9cbd7067ae28cded 100644 > --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi > @@ -1939,6 +1939,36 @@ mmss_noc: interconnect@1780000 { > #interconnect-cells = <2>; > }; > > + cryptobam: dma-controller@1dc4000 { > + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; > + reg = <0x0 0x01dc4000 0x0 0x28000>; > + > + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; > + > + #dma-cells = <1>; > + > + iommus = <&apps_smmu 0x480 0>, > + <&apps_smmu 0x481 0>; Should be equivalent to iommus = <&apps_smmu 0x480 0x1>? > + > + qcom,ee = <0>; > + qcom,controlled-remotely; If you don't have clocks here, you need to provide num-channels and qcom,num-ees. Otherwise, there is a risk this will crash if the BAM is not up while being probed. Thanks, Stephan
On Thu, Jan 16, 2025 at 9:06 AM PST, Stephan Gerhold wrote: > On Mon, Jan 13, 2025 at 01:16:22PM -0800, Melody Olvera wrote: > > From: Gaurav Kashyap <quic_gaurkash@quicinc.com> > > > > Add the QCE and Crypto BAM DMA nodes. > > > > Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com> > > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> > > --- > > arch/arm64/boot/dts/qcom/sm8750.dtsi | 30 > > ++++++++++++++++++++++++++++++ > > 1 file changed, 30 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi > > b/arch/arm64/boot/dts/qcom/sm8750.dtsi > > index > > > 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..1ddb33ea83885e73bf15244c > 9cbd > > 7067ae28cded 100644 > > --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi > > @@ -1939,6 +1939,36 @@ mmss_noc: interconnect@1780000 { > > #interconnect-cells = <2>; > > }; > > > > + cryptobam: dma-controller@1dc4000 { > > + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; > > + reg = <0x0 0x01dc4000 0x0 0x28000>; > > + > > + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; > > + > > + #dma-cells = <1>; > > + > > + iommus = <&apps_smmu 0x480 0>, > > + <&apps_smmu 0x481 0>; > > Should be equivalent to iommus = <&apps_smmu 0x480 0x1>? > Hello Stephan, we tried this out internally, and the use case was not functional. The masks are explicitly mentioned in our hardware documents and we are just following that. So, we are looking to keep it the same. > > + > > + qcom,ee = <0>; > > + qcom,controlled-remotely; > > If you don't have clocks here, you need to provide num-channels and > qcom,num-ees. Otherwise, there is a risk this will crash if the BAM is not up > while being probed. > Ack. > Thanks, > Stephan Regards, Gaurav
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..1ddb33ea83885e73bf15244c9cbd7067ae28cded 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -1939,6 +1939,36 @@ mmss_noc: interconnect@1780000 { #interconnect-cells = <2>; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + + #dma-cells = <1>; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + + qcom,ee = <0>; + qcom,controlled-remotely; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm8750-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>;