| Message ID | 20250114183005.2761213-2-niklas.soderlund+renesas@ragnatech.se (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | clk: renesas: gen4: Add ISP core clocks | expand |
On Tue, Jan 14, 2025 at 7:30 PM Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> wrote: > Add the ISP core modules clock for Renesas R-Car V3U. > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk for v6.15. Gr{oetje,eeting}s, Geert
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index 4a5b4e2afa92..1be7b9592aa6 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -138,6 +138,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { + DEF_MOD("isp0", 16, R8A779A0_CLK_S1D1), + DEF_MOD("isp1", 17, R8A779A0_CLK_S1D1), + DEF_MOD("isp2", 18, R8A779A0_CLK_S1D1), + DEF_MOD("isp3", 19, R8A779A0_CLK_S1D1), DEF_MOD("avb0", 211, R8A779A0_CLK_S3D2), DEF_MOD("avb1", 212, R8A779A0_CLK_S3D2), DEF_MOD("avb2", 213, R8A779A0_CLK_S3D2),
Add the ISP core modules clock for Renesas R-Car V3U. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> --- drivers/clk/renesas/r8a779a0-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+)