| Message ID | 20250116-cluster-hci-broken-v2-1-fc52cfb7a19e@bootlin.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | MIPS: Allow using multi-cluster with a broken HCI. | expand |
On Thu, Jan 16, 2025 at 11:59:19AM +0100, Gregory CLEMENT wrote: > From: Jiaxun Yang <jiaxun.yang@flygoat.com> > > Add devicetree binding documentation for MIPS Coherence Manager. > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> > --- > .../devicetree/bindings/mips/mti,mips-cm.yaml | 38 ++++++++++++++++++++++ > 1 file changed, 38 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml b/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..9f500804737d23e19f50a9326168686c05d3a54e > --- /dev/null > +++ b/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml > @@ -0,0 +1,38 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mips/mti,mips-cm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MIPS Coherence Manager > + > +description: | Don't need '|'. > + Defines a location of the MIPS Coherence Manager registers. Say what the h/w block does. > + > +maintainers: > + - Jiaxun Yang <jiaxun.yang@flygoat.com> > + > +properties: > + compatible: > + const: mti,mips-cm Convince me a genericish compatible is okay here. > + > + reg: > + description: > + Base address and size of an unoccupied region in system's MMIO address > + space, which will be used to map the MIPS CM global control registers > + block. It is conventionally decided by the system integrator. What is decided? The address? That's not relevant. > + maxItems: 1 > + > +required: > + - compatible > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + coherency-manager@1fbf8000 { > + compatible = "mti,mips-cm"; > + reg = <0x1bde8000 0x8000>; > + }; > +... > > -- > 2.45.2 >
Hi Rob, > On Thu, Jan 16, 2025 at 11:59:19AM +0100, Gregory CLEMENT wrote: >> From: Jiaxun Yang <jiaxun.yang@flygoat.com> >> >> Add devicetree binding documentation for MIPS Coherence Manager. >> >> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> >> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> >> --- >> .../devicetree/bindings/mips/mti,mips-cm.yaml | 38 ++++++++++++++++++++++ >> 1 file changed, 38 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml b/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml >> new file mode 100644 >> index 0000000000000000000000000000000000000000..9f500804737d23e19f50a9326168686c05d3a54e >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml >> @@ -0,0 +1,38 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/mips/mti,mips-cm.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: MIPS Coherence Manager >> + >> +description: | > > Don't need '|'. OK > >> + Defines a location of the MIPS Coherence Manager registers. > > Say what the h/w block does. Managing coherency ? :) However, more seriously, I can provide additional details based on what I have written in my previous emails. > >> + >> +maintainers: >> + - Jiaxun Yang <jiaxun.yang@flygoat.com> >> + >> +properties: >> + compatible: >> + const: mti,mips-cm > > Convince me a genericish compatible is okay here. well this componenant is really named Coherence Manager in the MIPS related document. For example in p4 of https://training.mips.com/cps_mips/PDF/CPS_Introduction.pdf and also https://training.mips.com/cps_mips/PDF/Coherency_Manager.pdf. > >> + >> + reg: >> + description: >> + Base address and size of an unoccupied region in system's MMIO address >> + space, which will be used to map the MIPS CM global control registers >> + block. It is conventionally decided by the system integrator. > > What is decided? The address? That's not relevant. Since reusing the description from Jiaxun, I'm unable to speak on his behalf. From my perspective, it simply implies that the value to be written should originate from the datasheet of the System-on-Chip (SoC), as the address is is specific to the integration into a given SoC. Gregory
diff --git a/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml b/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml new file mode 100644 index 0000000000000000000000000000000000000000..9f500804737d23e19f50a9326168686c05d3a54e --- /dev/null +++ b/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/mti,mips-cm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS Coherence Manager + +description: | + Defines a location of the MIPS Coherence Manager registers. + +maintainers: + - Jiaxun Yang <jiaxun.yang@flygoat.com> + +properties: + compatible: + const: mti,mips-cm + + reg: + description: + Base address and size of an unoccupied region in system's MMIO address + space, which will be used to map the MIPS CM global control registers + block. It is conventionally decided by the system integrator. + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + coherency-manager@1fbf8000 { + compatible = "mti,mips-cm"; + reg = <0x1bde8000 0x8000>; + }; +...