| Message ID | 20250122213427.28169-1-jorcrous@amazon.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | clk: qcom: camcc-sm8250: Use clk_rcg2_shared_ops for some RCGs | expand |
On Wed, Jan 22, 2025 at 09:34:27PM +0000, Jordan Crouse wrote: > Update some RCGs on the sm8250 camera clock controller to use > clk_rcg2_shared_ops. The shared_ops ensure the RCGs get parked > to the XO during clock disable to prevent the clocks from locking up > when the GDSC is enabled. These mirror similar fixes for other controllers > such as commit 8d4025943e13 ("clk: qcom: camcc-sc7180: Use runtime PM ops > instead of clk ones"). I'm not sure, how the mentioned commit is relevant to this fix. Did you mean e5c359f70e4b ("clk: qcom: camcc: Update the clock ops for the SC7180")? > > Signed-off-by: Jordan Crouse <jorcrous@amazon.com> > --- > > drivers/clk/qcom/camcc-sm8250.c | 56 ++++++++++++++++----------------- > 1 file changed, 28 insertions(+), 28 deletions(-) > > diff --git a/drivers/clk/qcom/camcc-sm8250.c b/drivers/clk/qcom/camcc-sm8250.c > index 34d2f17520dc..450ddbebd35f 100644 > --- a/drivers/clk/qcom/camcc-sm8250.c > +++ b/drivers/clk/qcom/camcc-sm8250.c > @@ -411,7 +411,7 @@ static struct clk_rcg2 cam_cc_bps_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; >
On Thu, Jan 23, 2025 at 12:12:46AM +0200, Dmitry Baryshkov wrote: > CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you can confirm the sender and know the content is safe. > > > > On Wed, Jan 22, 2025 at 09:34:27PM +0000, Jordan Crouse wrote: > > Update some RCGs on the sm8250 camera clock controller to use > > clk_rcg2_shared_ops. The shared_ops ensure the RCGs get parked > > to the XO during clock disable to prevent the clocks from locking up > > when the GDSC is enabled. These mirror similar fixes for other controllers > > such as commit 8d4025943e13 ("clk: qcom: camcc-sc7180: Use runtime PM ops > > instead of clk ones"). > > I'm not sure, how the mentioned commit is relevant to this fix. > Did you mean e5c359f70e4b ("clk: qcom: camcc: Update the clock ops for the SC7180")? Oops, yep. Great catch. v2 coming. Jordan
On 22/01/2025 21:34, Jordan Crouse wrote: > Update some RCGs on the sm8250 camera clock controller to use > clk_rcg2_shared_ops. The shared_ops ensure the RCGs get parked > to the XO during clock disable to prevent the clocks from locking up > when the GDSC is enabled. These mirror similar fixes for other controllers > such as commit 8d4025943e13 ("clk: qcom: camcc-sc7180: Use runtime PM ops > instead of clk ones"). > > Signed-off-by: Jordan Crouse <jorcrous@amazon.com> > --- > > drivers/clk/qcom/camcc-sm8250.c | 56 ++++++++++++++++----------------- > 1 file changed, 28 insertions(+), 28 deletions(-) > > diff --git a/drivers/clk/qcom/camcc-sm8250.c b/drivers/clk/qcom/camcc-sm8250.c > index 34d2f17520dc..450ddbebd35f 100644 > --- a/drivers/clk/qcom/camcc-sm8250.c > +++ b/drivers/clk/qcom/camcc-sm8250.c > @@ -411,7 +411,7 @@ static struct clk_rcg2 cam_cc_bps_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -433,7 +433,7 @@ static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -454,7 +454,7 @@ static struct clk_rcg2 cam_cc_cci_0_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -469,7 +469,7 @@ static struct clk_rcg2 cam_cc_cci_1_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -490,7 +490,7 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -511,7 +511,7 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -526,7 +526,7 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -556,7 +556,7 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -571,7 +571,7 @@ static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -586,7 +586,7 @@ static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -611,7 +611,7 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -634,7 +634,7 @@ static struct clk_rcg2 cam_cc_fd_core_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -649,7 +649,7 @@ static struct clk_rcg2 cam_cc_icp_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -673,7 +673,7 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = { > .parent_data = cam_cc_parent_data_2, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -710,7 +710,7 @@ static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -734,7 +734,7 @@ static struct clk_rcg2 cam_cc_ife_1_clk_src = { > .parent_data = cam_cc_parent_data_3, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -749,7 +749,7 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -771,7 +771,7 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -786,7 +786,7 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -810,7 +810,7 @@ static struct clk_rcg2 cam_cc_ipe_0_clk_src = { > .parent_data = cam_cc_parent_data_4, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -825,7 +825,7 @@ static struct clk_rcg2 cam_cc_jpeg_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -847,7 +847,7 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = { > .parent_data = cam_cc_parent_data_1, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -862,7 +862,7 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = { > .parent_data = cam_cc_parent_data_1, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -877,7 +877,7 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = { > .parent_data = cam_cc_parent_data_1, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -892,7 +892,7 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = { > .parent_data = cam_cc_parent_data_1, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -907,7 +907,7 @@ static struct clk_rcg2 cam_cc_mclk4_clk_src = { > .parent_data = cam_cc_parent_data_1, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -922,7 +922,7 @@ static struct clk_rcg2 cam_cc_mclk5_clk_src = { > .parent_data = cam_cc_parent_data_1, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -993,7 +993,7 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { > .parent_data = cam_cc_parent_data_0, > .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
diff --git a/drivers/clk/qcom/camcc-sm8250.c b/drivers/clk/qcom/camcc-sm8250.c index 34d2f17520dc..450ddbebd35f 100644 --- a/drivers/clk/qcom/camcc-sm8250.c +++ b/drivers/clk/qcom/camcc-sm8250.c @@ -411,7 +411,7 @@ static struct clk_rcg2 cam_cc_bps_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -433,7 +433,7 @@ static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -454,7 +454,7 @@ static struct clk_rcg2 cam_cc_cci_0_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -469,7 +469,7 @@ static struct clk_rcg2 cam_cc_cci_1_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -490,7 +490,7 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -511,7 +511,7 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -526,7 +526,7 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -556,7 +556,7 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -571,7 +571,7 @@ static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -586,7 +586,7 @@ static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -611,7 +611,7 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -634,7 +634,7 @@ static struct clk_rcg2 cam_cc_fd_core_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -649,7 +649,7 @@ static struct clk_rcg2 cam_cc_icp_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -673,7 +673,7 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = { .parent_data = cam_cc_parent_data_2, .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -710,7 +710,7 @@ static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -734,7 +734,7 @@ static struct clk_rcg2 cam_cc_ife_1_clk_src = { .parent_data = cam_cc_parent_data_3, .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -749,7 +749,7 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -771,7 +771,7 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -786,7 +786,7 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -810,7 +810,7 @@ static struct clk_rcg2 cam_cc_ipe_0_clk_src = { .parent_data = cam_cc_parent_data_4, .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -825,7 +825,7 @@ static struct clk_rcg2 cam_cc_jpeg_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -847,7 +847,7 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = { .parent_data = cam_cc_parent_data_1, .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -862,7 +862,7 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = { .parent_data = cam_cc_parent_data_1, .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -877,7 +877,7 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = { .parent_data = cam_cc_parent_data_1, .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -892,7 +892,7 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = { .parent_data = cam_cc_parent_data_1, .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -907,7 +907,7 @@ static struct clk_rcg2 cam_cc_mclk4_clk_src = { .parent_data = cam_cc_parent_data_1, .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -922,7 +922,7 @@ static struct clk_rcg2 cam_cc_mclk5_clk_src = { .parent_data = cam_cc_parent_data_1, .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -993,7 +993,7 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, };
Update some RCGs on the sm8250 camera clock controller to use clk_rcg2_shared_ops. The shared_ops ensure the RCGs get parked to the XO during clock disable to prevent the clocks from locking up when the GDSC is enabled. These mirror similar fixes for other controllers such as commit 8d4025943e13 ("clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones"). Signed-off-by: Jordan Crouse <jorcrous@amazon.com> --- drivers/clk/qcom/camcc-sm8250.c | 56 ++++++++++++++++----------------- 1 file changed, 28 insertions(+), 28 deletions(-)