| Message ID | 20250122115120.2885015-2-claudiu.beznea.uj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Delegated to: | Nobuhiro Iwamatsu |
| Headers | show |
| Series | renesas: rzg3s: backport the RTC support | expand |
Hi Claudiu, Thanks for your patch. > -----Original Message----- > From: Claudiu <claudiu.beznea@tuxon.dev> > Sent: Wednesday, January 22, 2025 8:51 PM > To: iwamatsu nobuhiro(岩松 信洋 ○ＤＩＴＣ□ＤＩＴ○ＯＳＴ) > <nobuhiro1.iwamatsu@toshiba.co.jp>; pavel@denx.de > Cc: claudiu.beznea@tuxon.dev; cip-dev@lists.cip-project.org > Subject: [PATCH v6.1.y-cip 01/14] clk: Add Sunplus SP7021 clock driver > > From: Qin Jian <qinjian@cqplus1.com> > > commit d54c1fd4a51e8fbc7f9da86b0cd338a4f7cd2bb2 upstream. > > Add clock driver for Sunplus SP7021 SoC. > > Signed-off-by: Qin Jian <qinjian@cqplus1.com> > Link: > https://lore.kernel.org/r/20221219015130.42621-1-qinjian@cqplus1.com > Signed-off-by: Stephen Boyd <sboyd@kernel.org> > [claudiu.beznea: kept only the code from include/linux/clk-provider.h] I understand that the SP7021 driver itself is unrelated to Renesas SoCs or this patch series. However, would you consider applying the patch as is without deleting the driver? From what I've checked, there seems to be no problem with building the driver. However, there are several fixes available upstream, so you should consider applying these. As I've recorded here, the patch subject content and the commit content barely match. I think it's better to keep the modifications required to backport the patch to a minimum. > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > include/linux/clk-provider.h | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index > d2c799595d5e..53dd7c9dcc94 100644 > --- a/include/linux/clk-provider.h > +++ b/include/linux/clk-provider.h > @@ -606,6 +606,25 @@ struct clk *clk_register_gate(struct device *dev, const > char *name, > __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), > NULL, \ > NULL, (flags), (reg), (bit_idx), > \ > (clk_gate_flags), (lock)) > +/** > + * devm_clk_hw_register_gate_parent_data - register a gate clock with > +the > + * clock framework > + * @dev: device that is registering this clock > + * @name: name of this clock > + * @parent_data: parent clk data > + * @flags: framework-specific flags for this clock > + * @reg: register address to control gating of this clock > + * @bit_idx: which bit in the register controls gating of this clock > + * @clk_gate_flags: gate-specific flags for this clock > + * @lock: shared register lock for this clock */ #define > +devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags, \ > + reg, bit_idx, clk_gate_flags, > \ > + lock) > \ > + __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, > \ > + (parent_data), (flags), (reg), (bit_idx), \ > + (clk_gate_flags), (lock)) > + > void clk_unregister_gate(struct clk *clk); void > clk_hw_unregister_gate(struct clk_hw *hw); int clk_gate_is_enabled(struct > clk_hw *hw); > -- > 2.43.0 Best regards, Nobuhiro
Hi, Nobuhiro, On 23.01.2025 07:38, Nobuhiro Iwamatsu via lists.cip-project.org wrote: > Hi Claudiu, > > Thanks for your patch. > >> -----Original Message----- >> From: Claudiu <claudiu.beznea@tuxon.dev> >> Sent: Wednesday, January 22, 2025 8:51 PM >> To: iwamatsu nobuhiro(岩松 信洋 ○ＤＩＴＣ□ＤＩＴ○ＯＳＴ) >> <nobuhiro1.iwamatsu@toshiba.co.jp>; pavel@denx.de >> Cc: claudiu.beznea@tuxon.dev; cip-dev@lists.cip-project.org >> Subject: [PATCH v6.1.y-cip 01/14] clk: Add Sunplus SP7021 clock driver >> >> From: Qin Jian <qinjian@cqplus1.com> >> >> commit d54c1fd4a51e8fbc7f9da86b0cd338a4f7cd2bb2 upstream. >> >> Add clock driver for Sunplus SP7021 SoC. >> >> Signed-off-by: Qin Jian <qinjian@cqplus1.com> >> Link: >> https://lore.kernel.org/r/20221219015130.42621-1-qinjian@cqplus1.com >> Signed-off-by: Stephen Boyd <sboyd@kernel.org> >> [claudiu.beznea: kept only the code from include/linux/clk-provider.h] > > I understand that the SP7021 driver itself is unrelated to Renesas SoCs or this patch series. > However, would you consider applying the patch as is without deleting the driver? Sure! > > From what I've checked, there seems to be no problem with building the driver. > However, there are several fixes available upstream, so you should consider applying these. Ok, I'll keep the full content of this patch (in the next version) and along with it backport the fixes. Is it OK if I'll do it in the same series with the RTC support for the Renesas RZ/G3S SoC? Thank you, Claudiu > > As I've recorded here, the patch subject content and the commit content barely match. I think > it's better to keep the modifications required to backport the patch to a minimum. > >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> --- >> include/linux/clk-provider.h | 19 +++++++++++++++++++ >> 1 file changed, 19 insertions(+) >> >> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index >> d2c799595d5e..53dd7c9dcc94 100644 >> --- a/include/linux/clk-provider.h >> +++ b/include/linux/clk-provider.h >> @@ -606,6 +606,25 @@ struct clk *clk_register_gate(struct device *dev, const >> char *name, >> __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), >> NULL, \ >> NULL, (flags), (reg), (bit_idx), >> \ >> (clk_gate_flags), (lock)) >> +/** >> + * devm_clk_hw_register_gate_parent_data - register a gate clock with >> +the >> + * clock framework >> + * @dev: device that is registering this clock >> + * @name: name of this clock >> + * @parent_data: parent clk data >> + * @flags: framework-specific flags for this clock >> + * @reg: register address to control gating of this clock >> + * @bit_idx: which bit in the register controls gating of this clock >> + * @clk_gate_flags: gate-specific flags for this clock >> + * @lock: shared register lock for this clock */ #define >> +devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags, \ >> + reg, bit_idx, clk_gate_flags, >> \ >> + lock) >> \ >> + __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, >> \ >> + (parent_data), (flags), (reg), (bit_idx), \ >> + (clk_gate_flags), (lock)) >> + >> void clk_unregister_gate(struct clk *clk); void >> clk_hw_unregister_gate(struct clk_hw *hw); int clk_gate_is_enabled(struct >> clk_hw *hw); >> -- >> 2.43.0 > > Best regards, > Nobuhiro > > > > -=-=-=-=-=-=-=-=-=-=-=- > Links: You receive all messages sent to this group. > View/Reply Online (#17601): https://lists.cip-project.org/g/cip-dev/message/17601 > Mute This Topic: https://lists.cip-project.org/mt/110751143/8377987 > Group Owner: cip-dev+owner@lists.cip-project.org > Unsubscribe: https://lists.cip-project.org/g/cip-dev/leave/13165139/8377987/1773116124/xyzzy [claudiu.beznea@tuxon.dev] > -=-=-=-=-=-=-=-=-=-=-=- >
Hi! > > I understand that the SP7021 driver itself is unrelated to Renesas SoCs or this patch series. > > However, would you consider applying the patch as is without deleting the driver? > > Sure! That would be one option. Another would be to apply just the include/linux/clk-provider.h with different title/changelog, explaining this adds only generic function and where it is originally from. Best regards, Pavel
Hi, Pavel, On 23.01.2025 17:34, Pavel Machek wrote: > Hi! > >>> I understand that the SP7021 driver itself is unrelated to Renesas SoCs or this patch series. >>> However, would you consider applying the patch as is without deleting the driver? >> >> Sure! > > That would be one option. Another would be to apply just the > include/linux/clk-provider.h with different title/changelog, > explaining this adds only generic function and where it is originally > from. I'll go with this. Thank you, Claudiu > > Best regards, > Pavel
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index d2c799595d5e..53dd7c9dcc94 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -606,6 +606,25 @@ struct clk *clk_register_gate(struct device *dev, const char *name, __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ NULL, (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) +/** + * devm_clk_hw_register_gate_parent_data - register a gate clock with the + * clock framework + * @dev: device that is registering this clock + * @name: name of this clock + * @parent_data: parent clk data + * @flags: framework-specific flags for this clock + * @reg: register address to control gating of this clock + * @bit_idx: which bit in the register controls gating of this clock + * @clk_gate_flags: gate-specific flags for this clock + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags, \ + reg, bit_idx, clk_gate_flags, \ + lock) \ + __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \ + (parent_data), (flags), (reg), (bit_idx), \ + (clk_gate_flags), (lock)) + void clk_unregister_gate(struct clk *clk); void clk_hw_unregister_gate(struct clk_hw *hw); int clk_gate_is_enabled(struct clk_hw *hw);