| Message ID | ed109ed88a6ae3849871ec341cb5ab2088097dd3.1738327620.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915/dp: dsc fix, refactoring and cleanups | expand |
On Fri, Jan 31, 2025 at 02:49:55PM +0200, Jani Nikula wrote: > Add a platform independent helper for getting the supported DSC BPP step > for the link. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 21 ++++++++++++++++----- > 1 file changed, 16 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index ecf192262eb9..a7a5bb2075da 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2054,6 +2054,21 @@ static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) > return 27; > } > > +/* > + * Note: for pre-13 display you still need to check the validity of each step. > + */ > +static int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector) Nit: there was a guideline that these KMS objects should be passed around via non-const pointers vs. state pointers which should be const if possible. > +{ > + struct intel_display *display = to_intel_display(connector); > + u8 incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); > + > + if (DISPLAY_VER(display) < 14 || !incr) > + return fxp_q4_from_int(1); > + > + /* fxp q4 */ > + return 16 / incr; Nit: could've been fxp_q4_from_int(1) / incr; Regardless of the nits, patch looks ok: Reviewed-by: Imre Deak <imre.deak@intel.com> > +} > + > /* > * From a list of valid compressed bpps try different compressed bpp and find a > * suitable link configuration that can support it. > @@ -2110,16 +2125,12 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp, > int timeslots) > { > struct intel_display *display = to_intel_display(intel_dp); > - u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); > int output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); > u16 compressed_bppx16; > u8 bppx16_step; > int ret; > > - if (DISPLAY_VER(display) < 14 || bppx16_incr <= 1) > - bppx16_step = 16; > - else > - bppx16_step = 16 / bppx16_incr; > + bppx16_step = intel_dp_dsc_bpp_step_x16(connector); > > /* Compressed BPP should be less than the Input DSC bpp */ > dsc_max_bpp = min(dsc_max_bpp << 4, (output_bpp << 4) - bppx16_step); > -- > 2.39.5 >
On Fri, 31 Jan 2025, Imre Deak <imre.deak@intel.com> wrote: > On Fri, Jan 31, 2025 at 02:49:55PM +0200, Jani Nikula wrote: >> Add a platform independent helper for getting the supported DSC BPP step >> for the link. >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_dp.c | 21 ++++++++++++++++----- >> 1 file changed, 16 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c >> index ecf192262eb9..a7a5bb2075da 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dp.c >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c >> @@ -2054,6 +2054,21 @@ static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) >> return 27; >> } >> >> +/* >> + * Note: for pre-13 display you still need to check the validity of each step. >> + */ >> +static int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector) > > Nit: there was a guideline that these KMS objects should be passed around via > non-const pointers vs. state pointers which should be const if possible. At this point, xelpd_dsc_compute_link_config() only has the const variable available. This changes later in the series. > >> +{ >> + struct intel_display *display = to_intel_display(connector); >> + u8 incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); >> + >> + if (DISPLAY_VER(display) < 14 || !incr) >> + return fxp_q4_from_int(1); >> + >> + /* fxp q4 */ >> + return 16 / incr; > > Nit: could've been fxp_q4_from_int(1) / incr; Good point, will fix. > > Regardless of the nits, patch looks ok: > > Reviewed-by: Imre Deak <imre.deak@intel.com> Thanks! > >> +} >> + >> /* >> * From a list of valid compressed bpps try different compressed bpp and find a >> * suitable link configuration that can support it. >> @@ -2110,16 +2125,12 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp, >> int timeslots) >> { >> struct intel_display *display = to_intel_display(intel_dp); >> - u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); >> int output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); >> u16 compressed_bppx16; >> u8 bppx16_step; >> int ret; >> >> - if (DISPLAY_VER(display) < 14 || bppx16_incr <= 1) >> - bppx16_step = 16; >> - else >> - bppx16_step = 16 / bppx16_incr; >> + bppx16_step = intel_dp_dsc_bpp_step_x16(connector); >> >> /* Compressed BPP should be less than the Input DSC bpp */ >> dsc_max_bpp = min(dsc_max_bpp << 4, (output_bpp << 4) - bppx16_step); >> -- >> 2.39.5 >>
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index ecf192262eb9..a7a5bb2075da 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2054,6 +2054,21 @@ static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) return 27; } +/* + * Note: for pre-13 display you still need to check the validity of each step. + */ +static int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector) +{ + struct intel_display *display = to_intel_display(connector); + u8 incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); + + if (DISPLAY_VER(display) < 14 || !incr) + return fxp_q4_from_int(1); + + /* fxp q4 */ + return 16 / incr; +} + /* * From a list of valid compressed bpps try different compressed bpp and find a * suitable link configuration that can support it. @@ -2110,16 +2125,12 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp, int timeslots) { struct intel_display *display = to_intel_display(intel_dp); - u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); int output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); u16 compressed_bppx16; u8 bppx16_step; int ret; - if (DISPLAY_VER(display) < 14 || bppx16_incr <= 1) - bppx16_step = 16; - else - bppx16_step = 16 / bppx16_incr; + bppx16_step = intel_dp_dsc_bpp_step_x16(connector); /* Compressed BPP should be less than the Input DSC bpp */ dsc_max_bpp = min(dsc_max_bpp << 4, (output_bpp << 4) - bppx16_step);
Add a platform independent helper for getting the supported DSC BPP step for the link. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-)