| Message ID | 20250204060955.3546022-1-jamin_lin@aspeedtech.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v1,1/1] aspeed/soc: Support Non-maskable Interrupt for AST2700 | expand |
+ Philippe On 2/4/25 07:09, Jamin Lin wrote: > QEMU supports GICv3 Non-maskable Interrupt, adds to support Non-maskable > Interrupt for AST2700. > > Reference: > https://github.com/qemu/qemu/commit/b36a32ead > > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> > --- > hw/arm/aspeed_ast27x0.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c > index 4114e15ddd..361a054d46 100644 > --- a/hw/arm/aspeed_ast27x0.c > +++ b/hw/arm/aspeed_ast27x0.c > @@ -470,6 +470,10 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) > qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); > sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, > qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); > + sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus, > + qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); > + sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus, > + qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); > } > > return true;
On 4/2/25 07:09, Jamin Lin via wrote: > QEMU supports GICv3 Non-maskable Interrupt, adds to support Non-maskable > Interrupt for AST2700. > > Reference: > https://github.com/qemu/qemu/commit/b36a32ead > Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > hw/arm/aspeed_ast27x0.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c > index 4114e15ddd..361a054d46 100644 > --- a/hw/arm/aspeed_ast27x0.c > +++ b/hw/arm/aspeed_ast27x0.c > @@ -470,6 +470,10 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) > qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); > sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, > qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); > + sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus, > + qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); > + sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus, > + qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); > } Thank you!
On 2/4/25 07:09, Jamin Lin wrote: > QEMU supports GICv3 Non-maskable Interrupt, adds to support Non-maskable > Interrupt for AST2700. > > Reference: > https://github.com/qemu/qemu/commit/b36a32ead > > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Applied to aspeed-next. Thanks, C. > --- > hw/arm/aspeed_ast27x0.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c > index 4114e15ddd..361a054d46 100644 > --- a/hw/arm/aspeed_ast27x0.c > +++ b/hw/arm/aspeed_ast27x0.c > @@ -470,6 +470,10 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) > qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); > sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, > qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); > + sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus, > + qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); > + sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus, > + qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); > } > > return true;
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 4114e15ddd..361a054d46 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -470,6 +470,10 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); + sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); + sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); } return true;
QEMU supports GICv3 Non-maskable Interrupt, adds to support Non-maskable Interrupt for AST2700. Reference: https://github.com/qemu/qemu/commit/b36a32ead Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- hw/arm/aspeed_ast27x0.c | 4 ++++ 1 file changed, 4 insertions(+)