| Message ID | 20250203-drm-msm-phy-pll-cfg-reg-v2-3-862b136c5d22@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/msm/dsi/phy: Improvements around concurrent PHY_CMN_CLK_CFG[01] | expand |
On Mon, Feb 03, 2025 at 06:29:20PM +0100, Krzysztof Kozlowski wrote: > PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI > clock divider, source of bitclk and two for enabling the DSI PHY PLL > clocks. > > dsi_7nm_set_usecase() sets only the source of bitclk, so should leave > all other bits untouched. Use newly introduced > dsi_pll_cmn_clk_cfg1_update() to update respective bits without > overwriting the rest. > > Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index e26f53f7cde8f0f6419a633f5d39784dc2e5bb98..926fd8e3330b2cdfc69d1e0e5d3930abae77b7d8 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -616,7 +616,6 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy) > static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) > { > struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); > - void __iomem *base = phy->base; > u32 data = 0x0; /* internal PLL */ > > DBG("DSI PLL%d", pll_7nm->phy->id); > @@ -635,7 +634,7 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) > } > > /* set PLL src */ > - writel(data << 2, base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); > + dsi_pll_cmn_clk_cfg1_update(pll_7nm, GENMASK(3, 2), data << 2); The mask is not defined, still. > > return 0; > } > > -- > 2.43.0 >
On 03/02/2025 18:40, Dmitry Baryshkov wrote: > On Mon, Feb 03, 2025 at 06:29:20PM +0100, Krzysztof Kozlowski wrote: >> PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI >> clock divider, source of bitclk and two for enabling the DSI PHY PLL >> clocks. >> >> dsi_7nm_set_usecase() sets only the source of bitclk, so should leave >> all other bits untouched. Use newly introduced >> dsi_pll_cmn_clk_cfg1_update() to update respective bits without >> overwriting the rest. >> >> Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> --- >> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 +-- >> 1 file changed, 1 insertion(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >> index e26f53f7cde8f0f6419a633f5d39784dc2e5bb98..926fd8e3330b2cdfc69d1e0e5d3930abae77b7d8 100644 >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >> @@ -616,7 +616,6 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy) >> static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) >> { >> struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); >> - void __iomem *base = phy->base; >> u32 data = 0x0; /* internal PLL */ >> >> DBG("DSI PLL%d", pll_7nm->phy->id); >> @@ -635,7 +634,7 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) >> } >> >> /* set PLL src */ >> - writel(data << 2, base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); >> + dsi_pll_cmn_clk_cfg1_update(pll_7nm, GENMASK(3, 2), data << 2); > > The mask is not defined, still. Why would it be? That's old/existing code. Commit is doing only one thing - fixing something. Not introducing some masks or defines and changing hard-coded values into defines. Best regards, Krzysztof
On Tue, Feb 04, 2025 at 10:22:19AM +0100, Krzysztof Kozlowski wrote: > On 03/02/2025 18:40, Dmitry Baryshkov wrote: > > On Mon, Feb 03, 2025 at 06:29:20PM +0100, Krzysztof Kozlowski wrote: > >> PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI > >> clock divider, source of bitclk and two for enabling the DSI PHY PLL > >> clocks. > >> > >> dsi_7nm_set_usecase() sets only the source of bitclk, so should leave > >> all other bits untouched. Use newly introduced > >> dsi_pll_cmn_clk_cfg1_update() to update respective bits without > >> overwriting the rest. > >> > >> Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") > >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > >> --- > >> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 +-- > >> 1 file changed, 1 insertion(+), 2 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > >> index e26f53f7cde8f0f6419a633f5d39784dc2e5bb98..926fd8e3330b2cdfc69d1e0e5d3930abae77b7d8 100644 > >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > >> @@ -616,7 +616,6 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy) > >> static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) > >> { > >> struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); > >> - void __iomem *base = phy->base; > >> u32 data = 0x0; /* internal PLL */ > >> > >> DBG("DSI PLL%d", pll_7nm->phy->id); > >> @@ -635,7 +634,7 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) > >> } > >> > >> /* set PLL src */ > >> - writel(data << 2, base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); > >> + dsi_pll_cmn_clk_cfg1_update(pll_7nm, GENMASK(3, 2), data << 2); > > > > The mask is not defined, still. > > Why would it be? That's old/existing code. Commit is doing only one > thing - fixing something. Not introducing some masks or defines and > changing hard-coded values into defines. GENMASK(3, 2) needs to be defined in the XML file. It was not there beforehand, you have just introduced it. > > Best regards, > Krzysztof
On 04/02/2025 15:27, Dmitry Baryshkov wrote: >>>> struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); >>>> - void __iomem *base = phy->base; >>>> u32 data = 0x0; /* internal PLL */ >>>> >>>> DBG("DSI PLL%d", pll_7nm->phy->id); >>>> @@ -635,7 +634,7 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) >>>> } >>>> >>>> /* set PLL src */ >>>> - writel(data << 2, base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); >>>> + dsi_pll_cmn_clk_cfg1_update(pll_7nm, GENMASK(3, 2), data << 2); >>> >>> The mask is not defined, still. >> >> Why would it be? That's old/existing code. Commit is doing only one >> thing - fixing something. Not introducing some masks or defines and >> changing hard-coded values into defines. > > GENMASK(3, 2) needs to be defined in the XML file. It was not there > beforehand, you have just introduced it. You are right. Best regards, Krzysztof
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index e26f53f7cde8f0f6419a633f5d39784dc2e5bb98..926fd8e3330b2cdfc69d1e0e5d3930abae77b7d8 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -616,7 +616,6 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy) static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) { struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); - void __iomem *base = phy->base; u32 data = 0x0; /* internal PLL */ DBG("DSI PLL%d", pll_7nm->phy->id); @@ -635,7 +634,7 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) } /* set PLL src */ - writel(data << 2, base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + dsi_pll_cmn_clk_cfg1_update(pll_7nm, GENMASK(3, 2), data << 2); return 0; }
PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI clock divider, source of bitclk and two for enabling the DSI PHY PLL clocks. dsi_7nm_set_usecase() sets only the source of bitclk, so should leave all other bits untouched. Use newly introduced dsi_pll_cmn_clk_cfg1_update() to update respective bits without overwriting the rest. Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)