| Message ID | 20250203205941.251754-1-gustavo.sousa@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915/dmc_wl: Track INITIATE_PM_DMD_REQ for DC5 | expand |
On Mon, 2025-02-03 at 17:58 -0300, Gustavo Sousa wrote: > The Bspec has been updated to include INITIATE_PM_DMD_REQ in the set of > register offsets that require the DMC wakelock for access during DC5. > Update our table accordingly. > > Bspec: 71583 > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dmc_wl.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c > index 43884740f8ea..86ba159b683c 100644 > --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c > +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c > @@ -102,6 +102,7 @@ static const struct intel_dmc_wl_range xe3lpd_dc5_dc6_dmc_ranges[] = { > { .start = 0x42088 }, /* CHICKEN_MISC_3 */ > { .start = 0x46160 }, /* CMTG_CLK_SEL */ > { .start = 0x8f000, .end = 0x8ffff }, /* Main DMC registers */ > + { .start = 0x45230 }, /* INITIATE_PM_DMD_REQ */ > > {}, > }; Matches the bspec. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> -- Cheers, Luca.
Quoting Patchwork (2025-02-04 01:07:43-03:00) >== Series Details == > >Series: drm/i915/dmc_wl: Track INITIATE_PM_DMD_REQ for DC5 >URL : https://patchwork.freedesktop.org/series/144278/ >State : failure > >== Summary == > >CI Bug Log - changes from CI_DRM_16058_full -> Patchwork_144278v1_full >==================================================== > >Summary >------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_144278v1_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_144278v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them > to document this new failure mode, which will reduce false positives in CI. > > > >Participating hosts (11 -> 11) >------------------------------ > > No changes in participating hosts > >Possible new issues >------------------- > > Here are the unknown changes that may have been introduced in Patchwork_144278v1_full: > >### IGT changes ### > >#### Possible regressions #### Hi, CI Team. > > * igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox: > - shard-mtlp: [PASS][1] -> [DMESG-WARN][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16058/shard-mtlp-4/igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144278v1/shard-mtlp-7/igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox.html This should probably be mapped to https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13193 > > * igt@i915_pm_rpm@system-suspend: > - shard-rkl: [PASS][3] -> [INCOMPLETE][4] > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16058/shard-rkl-3/igt@i915_pm_rpm@system-suspend.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144278v1/shard-rkl-5/igt@i915_pm_rpm@system-suspend.html > This patch simply adds an offset to a table and should not affect platforms with display version < 30, so none of the above failures are related to this patch. -- Gustavo Sousa
Quoting Luca Coelho (2025-02-04 05:46:38-03:00) >On Mon, 2025-02-03 at 17:58 -0300, Gustavo Sousa wrote: >> The Bspec has been updated to include INITIATE_PM_DMD_REQ in the set of >> register offsets that require the DMC wakelock for access during DC5. >> Update our table accordingly. >> >> Bspec: 71583 >> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_dmc_wl.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c >> index 43884740f8ea..86ba159b683c 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c >> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c >> @@ -102,6 +102,7 @@ static const struct intel_dmc_wl_range xe3lpd_dc5_dc6_dmc_ranges[] = { >> { .start = 0x42088 }, /* CHICKEN_MISC_3 */ >> { .start = 0x46160 }, /* CMTG_CLK_SEL */ >> { .start = 0x8f000, .end = 0x8ffff }, /* Main DMC registers */ >> + { .start = 0x45230 }, /* INITIATE_PM_DMD_REQ */ >> >> {}, >> }; > >Matches the bspec. > >Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Thanks for the review! Pushed to drm-intel-next. -- Gustavo Sousa
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c index 43884740f8ea..86ba159b683c 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c @@ -102,6 +102,7 @@ static const struct intel_dmc_wl_range xe3lpd_dc5_dc6_dmc_ranges[] = { { .start = 0x42088 }, /* CHICKEN_MISC_3 */ { .start = 0x46160 }, /* CMTG_CLK_SEL */ { .start = 0x8f000, .end = 0x8ffff }, /* Main DMC registers */ + { .start = 0x45230 }, /* INITIATE_PM_DMD_REQ */ {}, };
The Bspec has been updated to include INITIATE_PM_DMD_REQ in the set of register offsets that require the DMC wakelock for access during DC5. Update our table accordingly. Bspec: 71583 Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> --- drivers/gpu/drm/i915/display/intel_dmc_wl.c | 1 + 1 file changed, 1 insertion(+)