| Message ID | 20250129200221.2508101-10-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915/ddi: Fix/simplify port enabling/disabling | expand |
On Wed, 29 Jan 2025, Imre Deak <imre.deak@intel.com> wrote: > The functions disabling a port for MTL+ and earlier platforms only > differ by an extra step on MTL+ (to disable the D2D link) and the point > at which the port's idle state is waited for. Combine the two functions > accounting for the above differences, removing the duplication. > > Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 43 ++++-------------------- > 1 file changed, 7 insertions(+), 36 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 07188606a0177..73702ccbb3773 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3057,58 +3057,29 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) > port_name(port)); > } > > -static void mtl_disable_ddi_buf(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state) > +static void intel_disable_ddi_buf(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state) > { > + struct intel_display *display = to_intel_display(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > enum port port = encoder->port; > > - /* 3.b Clear DDI_CTL_DE Enable to 0. */ > intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); > > - /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ > - intel_wait_ddi_buf_idle(dev_priv, port); > + if (DISPLAY_VER(display) >= 14) > + intel_wait_ddi_buf_idle(dev_priv, port); > > - /* 3.d Disable D2D Link */ > mtl_ddi_disable_d2d_link(encoder); > > - /* 3.e Disable DP_TP_CTL */ > if (intel_crtc_has_dp_encoder(crtc_state)) { > intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), > DP_TP_CTL_ENABLE, 0); > } > -} > - > -static void disable_ddi_buf(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state) > -{ > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - enum port port = encoder->port; > - > - intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); > - > - if (intel_crtc_has_dp_encoder(crtc_state)) > - intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), > - DP_TP_CTL_ENABLE, 0); > > intel_ddi_disable_fec(encoder, crtc_state); > > - intel_wait_ddi_buf_idle(dev_priv, port); > -} > - > -static void intel_disable_ddi_buf(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state) > -{ > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - > - if (DISPLAY_VER(dev_priv) >= 14) { > - mtl_disable_ddi_buf(encoder, crtc_state); > - > - /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ > - intel_ddi_disable_fec(encoder, crtc_state); > - } else { > - disable_ddi_buf(encoder, crtc_state); > - } > + if (DISPLAY_VER(display) < 14) > + intel_wait_ddi_buf_idle(dev_priv, port); > > intel_ddi_wait_for_fec_status(encoder, crtc_state, false); > }
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 07188606a0177..73702ccbb3773 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3057,58 +3057,29 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) port_name(port)); } -static void mtl_disable_ddi_buf(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +static void intel_disable_ddi_buf(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - /* 3.b Clear DDI_CTL_DE Enable to 0. */ intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); - /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ - intel_wait_ddi_buf_idle(dev_priv, port); + if (DISPLAY_VER(display) >= 14) + intel_wait_ddi_buf_idle(dev_priv, port); - /* 3.d Disable D2D Link */ mtl_ddi_disable_d2d_link(encoder); - /* 3.e Disable DP_TP_CTL */ if (intel_crtc_has_dp_encoder(crtc_state)) { intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), DP_TP_CTL_ENABLE, 0); } -} - -static void disable_ddi_buf(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum port port = encoder->port; - - intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); - - if (intel_crtc_has_dp_encoder(crtc_state)) - intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), - DP_TP_CTL_ENABLE, 0); intel_ddi_disable_fec(encoder, crtc_state); - intel_wait_ddi_buf_idle(dev_priv, port); -} - -static void intel_disable_ddi_buf(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - - if (DISPLAY_VER(dev_priv) >= 14) { - mtl_disable_ddi_buf(encoder, crtc_state); - - /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ - intel_ddi_disable_fec(encoder, crtc_state); - } else { - disable_ddi_buf(encoder, crtc_state); - } + if (DISPLAY_VER(display) < 14) + intel_wait_ddi_buf_idle(dev_priv, port); intel_ddi_wait_for_fec_status(encoder, crtc_state, false); }
The functions disabling a port for MTL+ and earlier platforms only differ by an extra step on MTL+ (to disable the D2D link) and the point at which the port's idle state is waited for. Combine the two functions accounting for the above differences, removing the duplication. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 43 ++++-------------------- 1 file changed, 7 insertions(+), 36 deletions(-)