| Message ID | 20250209-expressatt-bam-v2-1-e6c01c5d8292@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2] ARM: dts: qcom: msm8960: Add BAM | expand |
On Sun, Feb 09, 2025 at 03:09:12PM -0800, Rudraksha Gupta wrote: > Copy bam nodes from qcom-ipq8064.dtsi and change > the reg values to match msm8960. > > Co-developed-by: Sam Day <me@samcday.com> > Signed-off-by: Sam Day <me@samcday.com> > Signed-off-by: Rudraksha Gupta <guptarud@gmail.com> > --- > Changes in v2: > - Reorganize sdcc{3,1}bam to be after sdcc{3,1} respectively > - Link to v1: https://lore.kernel.org/r/20250208-expressatt-bam-v1-1-8794ec853442@gmail.com > --- > arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 28 ++++++++++++++++++++++++++-- > 1 file changed, 26 insertions(+), 2 deletions(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 10.02.2025 12:09 AM, Rudraksha Gupta wrote: > Copy bam nodes from qcom-ipq8064.dtsi and change > the reg values to match msm8960. > > Co-developed-by: Sam Day <me@samcday.com> > Signed-off-by: Sam Day <me@samcday.com> > Signed-off-by: Rudraksha Gupta <guptarud@gmail.com> > --- > Changes in v2: > - Reorganize sdcc{3,1}bam to be after sdcc{3,1} respectively > - Link to v1: https://lore.kernel.org/r/20250208-expressatt-bam-v1-1-8794ec853442@gmail.com > --- > arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 28 ++++++++++++++++++++++++++-- > 1 file changed, 26 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi > index 865fe7cc39511d7cb9ec5c4b12100404f77e2989..a5ef9269b78b25b404e1ab11e6eff2639f16b446 100644 > --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi > +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi > @@ -279,7 +279,7 @@ sdcc3: mmc@12180000 { > compatible = "arm,pl18x", "arm,primecell"; > arm,primecell-periphid = <0x00051180>; > status = "disabled"; > - reg = <0x12180000 0x8000>; > + reg = <0x12180000 0x2000>; > interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; > clock-names = "mclk", "apb_pclk"; > @@ -289,13 +289,25 @@ sdcc3: mmc@12180000 { > max-frequency = <192000000>; > no-1-8-v; > vmmc-supply = <&vsdcc_fixed>; > + dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; > + dma-names = "tx", "rx"; > + }; > + > + sdcc3bam: dma-controller@12182000 { > + compatible = "qcom,bam-v1.3.0"; > + reg = <0x12182000 0x2000>; The BAM controller is 0x4000-long Otherwise, looks good Konrad
> > + sdcc3bam: dma-controller@12182000 { > > + compatible = "qcom,bam-v1.3.0"; > > + reg = <0x12182000 0x2000>; > > The BAM controller is 0x4000-long Seems like my device splats with this requested change: Diff: https://pastebin.com/AwzHPCLG Log: https://pastebin.com/WQswkndX > > Otherwise, looks good > > Konrad
On 12.02.2025 2:59 AM, Rudraksha Gupta wrote: >>> + sdcc3bam: dma-controller@12182000 { >>> + compatible = "qcom,bam-v1.3.0"; >>> + reg = <0x12182000 0x2000>; >> >> The BAM controller is 0x4000-long > > > Seems like my device splats with this requested change: > > Diff: https://pastebin.com/AwzHPCLG > Log: https://pastebin.com/WQswkndX Did you keep your changes that shortened the sd controllers address space? Konrad
> Did you keep your changes that shortened the sd controllers address space? No, I changed sdcc3, sdcc3bam, sdcc1, sdcc1bam from 0x2000 to 0x4000 (2nd param of reg) as you requested, however, I got a splat. Please let me know if I did anything wrong. Thanks. > > Konrad
On Thu, Feb 13, 2025 at 05:25:58PM -0800, Rudraksha Gupta wrote: > > Did you keep your changes that shortened the sd controllers address space? > > No, I changed sdcc3, sdcc3bam, sdcc1, sdcc1bam from 0x2000 to 0x4000 > (2nd param of reg) as you requested, however, I got a splat. > > Please let me know if I did anything wrong. Thanks. Konrad asked you to increase the size of the BAM devices. You've increased it for both BAM and SDCC controllers. Please revert the size of the arm,pl18x devices (sdcc1, sdcc3) to 0x2000. > > > > > Konrad
> Konrad asked you to increase the size of the BAM devices. You've > increased it for both BAM and SDCC controllers. Please revert the size > of the arm,pl18x devices (sdcc1, sdcc3) to 0x2000. Oh, I see now, thanks! Seems like I took Konrad's words literally. Sent in v3 :) > > > > > > > > > Konrad > > -- > With best wishes > Dmitry
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 865fe7cc39511d7cb9ec5c4b12100404f77e2989..a5ef9269b78b25b404e1ab11e6eff2639f16b446 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -279,7 +279,7 @@ sdcc3: mmc@12180000 { compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; status = "disabled"; - reg = <0x12180000 0x8000>; + reg = <0x12180000 0x2000>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; clock-names = "mclk", "apb_pclk"; @@ -289,13 +289,25 @@ sdcc3: mmc@12180000 { max-frequency = <192000000>; no-1-8-v; vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc3bam: dma-controller@12182000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x2000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc SDC3_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; }; sdcc1: mmc@12400000 { status = "disabled"; compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; + reg = <0x12400000 0x2000>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; clock-names = "mclk", "apb_pclk"; @@ -305,6 +317,18 @@ sdcc1: mmc@12400000 { cap-sd-highspeed; cap-mmc-highspeed; vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc1bam: dma-controller@12402000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x2000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; }; tcsr: syscon@1a400000 {