| Message ID | tencent_5360DA048EE5B8CF3104213F8D037C698208@qq.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | perf vendor events arm64: Add A720/A520 events/metrics | expand |
Hello, On Thu, Feb 13, 2025 at 11:11:01PM +0800, Yangyu Chen wrote: > This patchset adds the perf JSON files for the Cortex-A720 and Cortex-A520 > processors. Some events have been tested on Raxda Orion 6 with Cix P1 SoC > (8xA720 + 4xA520) running mainline Kernel with ACPI mode. I'm curious how the name of PMUs look like. It is cortex_a720 (or a520)? I remember there's a logic to check the length of hex digits at the end. Ian, are you ok with this? Thanks, Namhyung > > Yangyu Chen (2): > perf vendor events arm64: Add Cortex-A720 events/metrics > perf vendor events arm64: Add Cortex-A520 events/metrics > > .../arch/arm64/arm/cortex-a520/bus.json | 26 ++ > .../arch/arm64/arm/cortex-a520/exception.json | 18 + > .../arm64/arm/cortex-a520/fp_operation.json | 14 + > .../arch/arm64/arm/cortex-a520/general.json | 6 + > .../arch/arm64/arm/cortex-a520/l1d_cache.json | 50 ++ > .../arch/arm64/arm/cortex-a520/l1i_cache.json | 14 + > .../arch/arm64/arm/cortex-a520/l2_cache.json | 46 ++ > .../arch/arm64/arm/cortex-a520/l3_cache.json | 21 + > .../arch/arm64/arm/cortex-a520/ll_cache.json | 10 + > .../arch/arm64/arm/cortex-a520/memory.json | 58 +++ > .../arch/arm64/arm/cortex-a520/metrics.json | 373 +++++++++++++++ > .../arch/arm64/arm/cortex-a520/pmu.json | 8 + > .../arch/arm64/arm/cortex-a520/retired.json | 90 ++++ > .../arm64/arm/cortex-a520/spec_operation.json | 70 +++ > .../arch/arm64/arm/cortex-a520/stall.json | 82 ++++ > .../arch/arm64/arm/cortex-a520/sve.json | 22 + > .../arch/arm64/arm/cortex-a520/tlb.json | 78 ++++ > .../arch/arm64/arm/cortex-a520/trace.json | 32 ++ > .../arch/arm64/arm/cortex-a720/bus.json | 18 + > .../arch/arm64/arm/cortex-a720/exception.json | 62 +++ > .../arm64/arm/cortex-a720/fp_operation.json | 22 + > .../arch/arm64/arm/cortex-a720/general.json | 10 + > .../arch/arm64/arm/cortex-a720/l1d_cache.json | 50 ++ > .../arch/arm64/arm/cortex-a720/l1i_cache.json | 14 + > .../arch/arm64/arm/cortex-a720/l2_cache.json | 62 +++ > .../arch/arm64/arm/cortex-a720/l3_cache.json | 22 + > .../arch/arm64/arm/cortex-a720/ll_cache.json | 10 + > .../arch/arm64/arm/cortex-a720/memory.json | 54 +++ > .../arch/arm64/arm/cortex-a720/metrics.json | 436 ++++++++++++++++++ > .../arch/arm64/arm/cortex-a720/pmu.json | 8 + > .../arch/arm64/arm/cortex-a720/retired.json | 90 ++++ > .../arch/arm64/arm/cortex-a720/spe.json | 42 ++ > .../arm64/arm/cortex-a720/spec_operation.json | 90 ++++ > .../arch/arm64/arm/cortex-a720/stall.json | 82 ++++ > .../arch/arm64/arm/cortex-a720/sve.json | 50 ++ > .../arch/arm64/arm/cortex-a720/tlb.json | 74 +++ > .../arch/arm64/arm/cortex-a720/trace.json | 32 ++ > .../arch/arm64/common-and-microarch.json | 15 + > tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 + > 39 files changed, 2263 insertions(+) > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/bus.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/exception.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/fp_operation.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/general.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l1d_cache.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l1i_cache.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l2_cache.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l3_cache.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/ll_cache.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/memory.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/metrics.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/pmu.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/retired.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/spec_operation.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/stall.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/sve.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/tlb.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/trace.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/bus.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/exception.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/fp_operation.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/general.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l1d_cache.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l1i_cache.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l2_cache.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l3_cache.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/ll_cache.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/memory.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/metrics.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/pmu.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/retired.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/spe.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/spec_operation.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/stall.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/sve.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/tlb.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/trace.json > > -- > 2.47.2 >
> On 14 Feb 2025, at 09:12, Namhyung Kim <namhyung@kernel.org> wrote: > > Hello, > > On Thu, Feb 13, 2025 at 11:11:01PM +0800, Yangyu Chen wrote: >> This patchset adds the perf JSON files for the Cortex-A720 and Cortex-A520 >> processors. Some events have been tested on Raxda Orion 6 with Cix P1 SoC >> (8xA720 + 4xA520) running mainline Kernel with ACPI mode. > > I'm curious how the name of PMUs look like. It is cortex_a720 (or a520)? The name of PMUs comes from Arm's documentation. I have included these links in each patch. > I remember there's a logic to check the length of hex digits at the end. > Could you provide more details about this? > Ian, are you ok with this? > > Thanks, > Namhyung > >> >> Yangyu Chen (2): >> perf vendor events arm64: Add Cortex-A720 events/metrics >> perf vendor events arm64: Add Cortex-A520 events/metrics >> >> .../arch/arm64/arm/cortex-a520/bus.json | 26 ++ >> .../arch/arm64/arm/cortex-a520/exception.json | 18 + >> .../arm64/arm/cortex-a520/fp_operation.json | 14 + >> .../arch/arm64/arm/cortex-a520/general.json | 6 + >> .../arch/arm64/arm/cortex-a520/l1d_cache.json | 50 ++ >> .../arch/arm64/arm/cortex-a520/l1i_cache.json | 14 + >> .../arch/arm64/arm/cortex-a520/l2_cache.json | 46 ++ >> .../arch/arm64/arm/cortex-a520/l3_cache.json | 21 + >> .../arch/arm64/arm/cortex-a520/ll_cache.json | 10 + >> .../arch/arm64/arm/cortex-a520/memory.json | 58 +++ >> .../arch/arm64/arm/cortex-a520/metrics.json | 373 +++++++++++++++ >> .../arch/arm64/arm/cortex-a520/pmu.json | 8 + >> .../arch/arm64/arm/cortex-a520/retired.json | 90 ++++ >> .../arm64/arm/cortex-a520/spec_operation.json | 70 +++ >> .../arch/arm64/arm/cortex-a520/stall.json | 82 ++++ >> .../arch/arm64/arm/cortex-a520/sve.json | 22 + >> .../arch/arm64/arm/cortex-a520/tlb.json | 78 ++++ >> .../arch/arm64/arm/cortex-a520/trace.json | 32 ++ >> .../arch/arm64/arm/cortex-a720/bus.json | 18 + >> .../arch/arm64/arm/cortex-a720/exception.json | 62 +++ >> .../arm64/arm/cortex-a720/fp_operation.json | 22 + >> .../arch/arm64/arm/cortex-a720/general.json | 10 + >> .../arch/arm64/arm/cortex-a720/l1d_cache.json | 50 ++ >> .../arch/arm64/arm/cortex-a720/l1i_cache.json | 14 + >> .../arch/arm64/arm/cortex-a720/l2_cache.json | 62 +++ >> .../arch/arm64/arm/cortex-a720/l3_cache.json | 22 + >> .../arch/arm64/arm/cortex-a720/ll_cache.json | 10 + >> .../arch/arm64/arm/cortex-a720/memory.json | 54 +++ >> .../arch/arm64/arm/cortex-a720/metrics.json | 436 ++++++++++++++++++ >> .../arch/arm64/arm/cortex-a720/pmu.json | 8 + >> .../arch/arm64/arm/cortex-a720/retired.json | 90 ++++ >> .../arch/arm64/arm/cortex-a720/spe.json | 42 ++ >> .../arm64/arm/cortex-a720/spec_operation.json | 90 ++++ >> .../arch/arm64/arm/cortex-a720/stall.json | 82 ++++ >> .../arch/arm64/arm/cortex-a720/sve.json | 50 ++ >> .../arch/arm64/arm/cortex-a720/tlb.json | 74 +++ >> .../arch/arm64/arm/cortex-a720/trace.json | 32 ++ >> .../arch/arm64/common-and-microarch.json | 15 + >> tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 + >> 39 files changed, 2263 insertions(+) >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/bus.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/exception.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/fp_operation.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/general.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l1d_cache.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l1i_cache.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l2_cache.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l3_cache.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/ll_cache.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/memory.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/metrics.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/pmu.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/retired.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/spec_operation.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/stall.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/sve.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/tlb.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/trace.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/bus.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/exception.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/fp_operation.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/general.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l1d_cache.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l1i_cache.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l2_cache.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l3_cache.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/ll_cache.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/memory.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/metrics.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/pmu.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/retired.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/spe.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/spec_operation.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/stall.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/sve.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/tlb.json >> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/trace.json >> >> -- >> 2.47.2 >>
On 14/02/2025 5:49 am, Yangyu Chen wrote: > > >> On 14 Feb 2025, at 09:12, Namhyung Kim <namhyung@kernel.org> wrote: >> >> Hello, >> >> On Thu, Feb 13, 2025 at 11:11:01PM +0800, Yangyu Chen wrote: >>> This patchset adds the perf JSON files for the Cortex-A720 and Cortex-A520 >>> processors. Some events have been tested on Raxda Orion 6 with Cix P1 SoC >>> (8xA720 + 4xA520) running mainline Kernel with ACPI mode. >> >> I'm curious how the name of PMUs look like. It is cortex_a720 (or a520)? > > The name of PMUs comes from Arm's documentation. I have included these > links in each patch. > >> I remember there's a logic to check the length of hex digits at the end. >> > > Could you provide more details about this? > >> Ian, are you ok with this? >> I think they wouldn't be merged because they're core PMUs, so should be fine? Even though they would otherwise be merged because they're more than 3 hex digits. >> Thanks, >> Namhyung >> >>> >>> Yangyu Chen (2): >>> perf vendor events arm64: Add Cortex-A720 events/metrics >>> perf vendor events arm64: Add Cortex-A520 events/metrics >>> >>> .../arch/arm64/arm/cortex-a520/bus.json | 26 ++ >>> .../arch/arm64/arm/cortex-a520/exception.json | 18 + >>> .../arm64/arm/cortex-a520/fp_operation.json | 14 + >>> .../arch/arm64/arm/cortex-a520/general.json | 6 + >>> .../arch/arm64/arm/cortex-a520/l1d_cache.json | 50 ++ >>> .../arch/arm64/arm/cortex-a520/l1i_cache.json | 14 + >>> .../arch/arm64/arm/cortex-a520/l2_cache.json | 46 ++ >>> .../arch/arm64/arm/cortex-a520/l3_cache.json | 21 + >>> .../arch/arm64/arm/cortex-a520/ll_cache.json | 10 + >>> .../arch/arm64/arm/cortex-a520/memory.json | 58 +++ >>> .../arch/arm64/arm/cortex-a520/metrics.json | 373 +++++++++++++++ >>> .../arch/arm64/arm/cortex-a520/pmu.json | 8 + >>> .../arch/arm64/arm/cortex-a520/retired.json | 90 ++++ >>> .../arm64/arm/cortex-a520/spec_operation.json | 70 +++ >>> .../arch/arm64/arm/cortex-a520/stall.json | 82 ++++ >>> .../arch/arm64/arm/cortex-a520/sve.json | 22 + >>> .../arch/arm64/arm/cortex-a520/tlb.json | 78 ++++ >>> .../arch/arm64/arm/cortex-a520/trace.json | 32 ++ >>> .../arch/arm64/arm/cortex-a720/bus.json | 18 + >>> .../arch/arm64/arm/cortex-a720/exception.json | 62 +++ >>> .../arm64/arm/cortex-a720/fp_operation.json | 22 + >>> .../arch/arm64/arm/cortex-a720/general.json | 10 + >>> .../arch/arm64/arm/cortex-a720/l1d_cache.json | 50 ++ >>> .../arch/arm64/arm/cortex-a720/l1i_cache.json | 14 + >>> .../arch/arm64/arm/cortex-a720/l2_cache.json | 62 +++ >>> .../arch/arm64/arm/cortex-a720/l3_cache.json | 22 + >>> .../arch/arm64/arm/cortex-a720/ll_cache.json | 10 + >>> .../arch/arm64/arm/cortex-a720/memory.json | 54 +++ >>> .../arch/arm64/arm/cortex-a720/metrics.json | 436 ++++++++++++++++++ >>> .../arch/arm64/arm/cortex-a720/pmu.json | 8 + >>> .../arch/arm64/arm/cortex-a720/retired.json | 90 ++++ >>> .../arch/arm64/arm/cortex-a720/spe.json | 42 ++ >>> .../arm64/arm/cortex-a720/spec_operation.json | 90 ++++ >>> .../arch/arm64/arm/cortex-a720/stall.json | 82 ++++ >>> .../arch/arm64/arm/cortex-a720/sve.json | 50 ++ >>> .../arch/arm64/arm/cortex-a720/tlb.json | 74 +++ >>> .../arch/arm64/arm/cortex-a720/trace.json | 32 ++ >>> .../arch/arm64/common-and-microarch.json | 15 + >>> tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 + >>> 39 files changed, 2263 insertions(+) >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/bus.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/exception.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/fp_operation.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/general.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l1d_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l1i_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l2_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l3_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/ll_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/memory.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/metrics.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/pmu.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/retired.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/spec_operation.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/stall.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/sve.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/tlb.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/trace.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/bus.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/exception.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/fp_operation.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/general.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l1d_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l1i_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l2_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l3_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/ll_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/memory.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/metrics.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/pmu.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/retired.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/spe.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/spec_operation.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/stall.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/sve.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/tlb.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/trace.json >>> >>> -- >>> 2.47.2 >>> >
On Fri, Feb 14, 2025 at 2:02 AM James Clark <james.clark@linaro.org> wrote: > > > > On 14/02/2025 5:49 am, Yangyu Chen wrote: > > > > > >> On 14 Feb 2025, at 09:12, Namhyung Kim <namhyung@kernel.org> wrote: > >> > >> Hello, > >> > >> On Thu, Feb 13, 2025 at 11:11:01PM +0800, Yangyu Chen wrote: > >>> This patchset adds the perf JSON files for the Cortex-A720 and Cortex-A520 > >>> processors. Some events have been tested on Raxda Orion 6 with Cix P1 SoC > >>> (8xA720 + 4xA520) running mainline Kernel with ACPI mode. > >> > >> I'm curious how the name of PMUs look like. It is cortex_a720 (or a520)? > > > > The name of PMUs comes from Arm's documentation. I have included these > > links in each patch. > > > >> I remember there's a logic to check the length of hex digits at the end. > >> > > > > Could you provide more details about this? > > > >> Ian, are you ok with this? > >> > > I think they wouldn't be merged because they're core PMUs, so should be > fine? Even though they would otherwise be merged because they're more > than 3 hex digits. Do we know the PMU names? If they are cortex_a520 and cortex_a720 then this comment at least reads a little stale: https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n76 ``` /* * There is a '_{num}' suffix. For decimal suffixes any length * will do, for hexadecimal ensure more than 2 hex digits so * that S390's cpum_cf PMU doesn't match. */ ``` James is right that core PMUs aren't put on the same list as uncore/other PMUs. Thanks, Ian > >> Thanks, > >> Namhyung > >> > >>> > >>> Yangyu Chen (2): > >>> perf vendor events arm64: Add Cortex-A720 events/metrics > >>> perf vendor events arm64: Add Cortex-A520 events/metrics > >>> > >>> .../arch/arm64/arm/cortex-a520/bus.json | 26 ++ > >>> .../arch/arm64/arm/cortex-a520/exception.json | 18 + > >>> .../arm64/arm/cortex-a520/fp_operation.json | 14 + > >>> .../arch/arm64/arm/cortex-a520/general.json | 6 + > >>> .../arch/arm64/arm/cortex-a520/l1d_cache.json | 50 ++ > >>> .../arch/arm64/arm/cortex-a520/l1i_cache.json | 14 + > >>> .../arch/arm64/arm/cortex-a520/l2_cache.json | 46 ++ > >>> .../arch/arm64/arm/cortex-a520/l3_cache.json | 21 + > >>> .../arch/arm64/arm/cortex-a520/ll_cache.json | 10 + > >>> .../arch/arm64/arm/cortex-a520/memory.json | 58 +++ > >>> .../arch/arm64/arm/cortex-a520/metrics.json | 373 +++++++++++++++ > >>> .../arch/arm64/arm/cortex-a520/pmu.json | 8 + > >>> .../arch/arm64/arm/cortex-a520/retired.json | 90 ++++ > >>> .../arm64/arm/cortex-a520/spec_operation.json | 70 +++ > >>> .../arch/arm64/arm/cortex-a520/stall.json | 82 ++++ > >>> .../arch/arm64/arm/cortex-a520/sve.json | 22 + > >>> .../arch/arm64/arm/cortex-a520/tlb.json | 78 ++++ > >>> .../arch/arm64/arm/cortex-a520/trace.json | 32 ++ > >>> .../arch/arm64/arm/cortex-a720/bus.json | 18 + > >>> .../arch/arm64/arm/cortex-a720/exception.json | 62 +++ > >>> .../arm64/arm/cortex-a720/fp_operation.json | 22 + > >>> .../arch/arm64/arm/cortex-a720/general.json | 10 + > >>> .../arch/arm64/arm/cortex-a720/l1d_cache.json | 50 ++ > >>> .../arch/arm64/arm/cortex-a720/l1i_cache.json | 14 + > >>> .../arch/arm64/arm/cortex-a720/l2_cache.json | 62 +++ > >>> .../arch/arm64/arm/cortex-a720/l3_cache.json | 22 + > >>> .../arch/arm64/arm/cortex-a720/ll_cache.json | 10 + > >>> .../arch/arm64/arm/cortex-a720/memory.json | 54 +++ > >>> .../arch/arm64/arm/cortex-a720/metrics.json | 436 ++++++++++++++++++ > >>> .../arch/arm64/arm/cortex-a720/pmu.json | 8 + > >>> .../arch/arm64/arm/cortex-a720/retired.json | 90 ++++ > >>> .../arch/arm64/arm/cortex-a720/spe.json | 42 ++ > >>> .../arm64/arm/cortex-a720/spec_operation.json | 90 ++++ > >>> .../arch/arm64/arm/cortex-a720/stall.json | 82 ++++ > >>> .../arch/arm64/arm/cortex-a720/sve.json | 50 ++ > >>> .../arch/arm64/arm/cortex-a720/tlb.json | 74 +++ > >>> .../arch/arm64/arm/cortex-a720/trace.json | 32 ++ > >>> .../arch/arm64/common-and-microarch.json | 15 + > >>> tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 + > >>> 39 files changed, 2263 insertions(+) > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/bus.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/exception.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/fp_operation.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/general.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l1d_cache.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l1i_cache.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l2_cache.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l3_cache.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/ll_cache.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/memory.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/metrics.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/pmu.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/retired.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/spec_operation.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/stall.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/sve.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/tlb.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/trace.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/bus.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/exception.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/fp_operation.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/general.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l1d_cache.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l1i_cache.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l2_cache.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l3_cache.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/ll_cache.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/memory.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/metrics.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/pmu.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/retired.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/spe.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/spec_operation.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/stall.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/sve.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/tlb.json > >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/trace.json > >>> > >>> -- > >>> 2.47.2 > >>> > > >
On 18/02/2025 12:41 am, Ian Rogers wrote: > On Fri, Feb 14, 2025 at 2:02 AM James Clark <james.clark@linaro.org> wrote: >> >> >> >> On 14/02/2025 5:49 am, Yangyu Chen wrote: >>> >>> >>>> On 14 Feb 2025, at 09:12, Namhyung Kim <namhyung@kernel.org> wrote: >>>> >>>> Hello, >>>> >>>> On Thu, Feb 13, 2025 at 11:11:01PM +0800, Yangyu Chen wrote: >>>>> This patchset adds the perf JSON files for the Cortex-A720 and Cortex-A520 >>>>> processors. Some events have been tested on Raxda Orion 6 with Cix P1 SoC >>>>> (8xA720 + 4xA520) running mainline Kernel with ACPI mode. >>>> >>>> I'm curious how the name of PMUs look like. It is cortex_a720 (or a520)? >>> >>> The name of PMUs comes from Arm's documentation. I have included these >>> links in each patch. >>> >>>> I remember there's a logic to check the length of hex digits at the end. >>>> >>> >>> Could you provide more details about this? >>> >>>> Ian, are you ok with this? >>>> >> >> I think they wouldn't be merged because they're core PMUs, so should be >> fine? Even though they would otherwise be merged because they're more >> than 3 hex digits. > > Do we know the PMU names? If they are cortex_a520 and cortex_a720 then It will be "armv9_cortex_a720" from this line: PMUV3_INIT_SIMPLE(armv9_cortex_a720) > this comment at least reads a little stale: > https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n76 > ``` > /* > * There is a '_{num}' suffix. For decimal suffixes any length > * will do, for hexadecimal ensure more than 2 hex digits so > * that S390's cpum_cf PMU doesn't match. > */ > ``` > James is right that core PMUs aren't put on the same list as uncore/other PMUs. > > Thanks, > Ian > >>>> Thanks, >>>> Namhyung >>>> >>>>> >>>>> Yangyu Chen (2): >>>>> perf vendor events arm64: Add Cortex-A720 events/metrics >>>>> perf vendor events arm64: Add Cortex-A520 events/metrics >>>>> >>>>> .../arch/arm64/arm/cortex-a520/bus.json | 26 ++ >>>>> .../arch/arm64/arm/cortex-a520/exception.json | 18 + >>>>> .../arm64/arm/cortex-a520/fp_operation.json | 14 + >>>>> .../arch/arm64/arm/cortex-a520/general.json | 6 + >>>>> .../arch/arm64/arm/cortex-a520/l1d_cache.json | 50 ++ >>>>> .../arch/arm64/arm/cortex-a520/l1i_cache.json | 14 + >>>>> .../arch/arm64/arm/cortex-a520/l2_cache.json | 46 ++ >>>>> .../arch/arm64/arm/cortex-a520/l3_cache.json | 21 + >>>>> .../arch/arm64/arm/cortex-a520/ll_cache.json | 10 + >>>>> .../arch/arm64/arm/cortex-a520/memory.json | 58 +++ >>>>> .../arch/arm64/arm/cortex-a520/metrics.json | 373 +++++++++++++++ >>>>> .../arch/arm64/arm/cortex-a520/pmu.json | 8 + >>>>> .../arch/arm64/arm/cortex-a520/retired.json | 90 ++++ >>>>> .../arm64/arm/cortex-a520/spec_operation.json | 70 +++ >>>>> .../arch/arm64/arm/cortex-a520/stall.json | 82 ++++ >>>>> .../arch/arm64/arm/cortex-a520/sve.json | 22 + >>>>> .../arch/arm64/arm/cortex-a520/tlb.json | 78 ++++ >>>>> .../arch/arm64/arm/cortex-a520/trace.json | 32 ++ >>>>> .../arch/arm64/arm/cortex-a720/bus.json | 18 + >>>>> .../arch/arm64/arm/cortex-a720/exception.json | 62 +++ >>>>> .../arm64/arm/cortex-a720/fp_operation.json | 22 + >>>>> .../arch/arm64/arm/cortex-a720/general.json | 10 + >>>>> .../arch/arm64/arm/cortex-a720/l1d_cache.json | 50 ++ >>>>> .../arch/arm64/arm/cortex-a720/l1i_cache.json | 14 + >>>>> .../arch/arm64/arm/cortex-a720/l2_cache.json | 62 +++ >>>>> .../arch/arm64/arm/cortex-a720/l3_cache.json | 22 + >>>>> .../arch/arm64/arm/cortex-a720/ll_cache.json | 10 + >>>>> .../arch/arm64/arm/cortex-a720/memory.json | 54 +++ >>>>> .../arch/arm64/arm/cortex-a720/metrics.json | 436 ++++++++++++++++++ >>>>> .../arch/arm64/arm/cortex-a720/pmu.json | 8 + >>>>> .../arch/arm64/arm/cortex-a720/retired.json | 90 ++++ >>>>> .../arch/arm64/arm/cortex-a720/spe.json | 42 ++ >>>>> .../arm64/arm/cortex-a720/spec_operation.json | 90 ++++ >>>>> .../arch/arm64/arm/cortex-a720/stall.json | 82 ++++ >>>>> .../arch/arm64/arm/cortex-a720/sve.json | 50 ++ >>>>> .../arch/arm64/arm/cortex-a720/tlb.json | 74 +++ >>>>> .../arch/arm64/arm/cortex-a720/trace.json | 32 ++ >>>>> .../arch/arm64/common-and-microarch.json | 15 + >>>>> tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 + >>>>> 39 files changed, 2263 insertions(+) >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/bus.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/exception.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/fp_operation.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/general.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l1d_cache.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l1i_cache.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l2_cache.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l3_cache.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/ll_cache.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/memory.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/metrics.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/pmu.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/retired.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/spec_operation.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/stall.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/sve.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/tlb.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/trace.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/bus.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/exception.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/fp_operation.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/general.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l1d_cache.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l1i_cache.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l2_cache.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l3_cache.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/ll_cache.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/memory.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/metrics.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/pmu.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/retired.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/spe.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/spec_operation.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/stall.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/sve.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/tlb.json >>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/trace.json >>>>> >>>>> -- >>>>> 2.47.2 >>>>> >>> >>
On Tue, Feb 18, 2025 at 09:30:23AM +0000, James Clark wrote: > > > On 18/02/2025 12:41 am, Ian Rogers wrote: > > On Fri, Feb 14, 2025 at 2:02 AM James Clark <james.clark@linaro.org> wrote: > > > > > > > > > > > > On 14/02/2025 5:49 am, Yangyu Chen wrote: > > > > > > > > > > > > > On 14 Feb 2025, at 09:12, Namhyung Kim <namhyung@kernel.org> wrote: > > > > > > > > > > Hello, > > > > > > > > > > On Thu, Feb 13, 2025 at 11:11:01PM +0800, Yangyu Chen wrote: > > > > > > This patchset adds the perf JSON files for the Cortex-A720 and Cortex-A520 > > > > > > processors. Some events have been tested on Raxda Orion 6 with Cix P1 SoC > > > > > > (8xA720 + 4xA520) running mainline Kernel with ACPI mode. > > > > > > > > > > I'm curious how the name of PMUs look like. It is cortex_a720 (or a520)? > > > > > > > > The name of PMUs comes from Arm's documentation. I have included these > > > > links in each patch. > > > > > > > > > I remember there's a logic to check the length of hex digits at the end. > > > > > > > > > > > > > Could you provide more details about this? > > > > > > > > > Ian, are you ok with this? > > > > > > > > > > > I think they wouldn't be merged because they're core PMUs, so should be > > > fine? Even though they would otherwise be merged because they're more > > > than 3 hex digits. > > > > Do we know the PMU names? If they are cortex_a520 and cortex_a720 then > > It will be "armv9_cortex_a720" from this line: > > PMUV3_INIT_SIMPLE(armv9_cortex_a720) I see, thanks! > > > this comment at least reads a little stale: > > https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n76 > > ``` > > /* > > * There is a '_{num}' suffix. For decimal suffixes any length > > * will do, for hexadecimal ensure more than 2 hex digits so > > * that S390's cpum_cf PMU doesn't match. > > */ > > ``` > > James is right that core PMUs aren't put on the same list as uncore/other PMUs. Ok, then I guess we're good. Thanks, Namhyung
On Tue, Feb 18, 2025 at 2:19 PM Namhyung Kim <namhyung@kernel.org> wrote: > > On Tue, Feb 18, 2025 at 09:30:23AM +0000, James Clark wrote: > > > > > > On 18/02/2025 12:41 am, Ian Rogers wrote: > > > On Fri, Feb 14, 2025 at 2:02 AM James Clark <james.clark@linaro.org> wrote: > > > > > > > > > > > > > > > > On 14/02/2025 5:49 am, Yangyu Chen wrote: > > > > > > > > > > > > > > > > On 14 Feb 2025, at 09:12, Namhyung Kim <namhyung@kernel.org> wrote: > > > > > > > > > > > > Hello, > > > > > > > > > > > > On Thu, Feb 13, 2025 at 11:11:01PM +0800, Yangyu Chen wrote: > > > > > > > This patchset adds the perf JSON files for the Cortex-A720 and Cortex-A520 > > > > > > > processors. Some events have been tested on Raxda Orion 6 with Cix P1 SoC > > > > > > > (8xA720 + 4xA520) running mainline Kernel with ACPI mode. > > > > > > > > > > > > I'm curious how the name of PMUs look like. It is cortex_a720 (or a520)? > > > > > > > > > > The name of PMUs comes from Arm's documentation. I have included these > > > > > links in each patch. > > > > > > > > > > > I remember there's a logic to check the length of hex digits at the end. > > > > > > > > > > > > > > > > Could you provide more details about this? > > > > > > > > > > > Ian, are you ok with this? > > > > > > > > > > > > > > I think they wouldn't be merged because they're core PMUs, so should be > > > > fine? Even though they would otherwise be merged because they're more > > > > than 3 hex digits. > > > > > > Do we know the PMU names? If they are cortex_a520 and cortex_a720 then > > > > It will be "armv9_cortex_a720" from this line: > > > > PMUV3_INIT_SIMPLE(armv9_cortex_a720) > > I see, thanks! > > > > > > this comment at least reads a little stale: > > > https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n76 > > > ``` > > > /* > > > * There is a '_{num}' suffix. For decimal suffixes any length > > > * will do, for hexadecimal ensure more than 2 hex digits so > > > * that S390's cpum_cf PMU doesn't match. > > > */ > > > ``` > > > James is right that core PMUs aren't put on the same list as uncore/other PMUs. > > Ok, then I guess we're good. I think you may be able to do things that look odd, like today the "i915" PMU can be called just "i", I think the a520/a720 naming will allow "armv9_cortex/cycles/" as an event name, then open it on two PMUs if they are present. We may only show one PMU in perf list as that code I think assumes they're the same PMU as they only differ by suffix: https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n384 I can imagine aggregation possibly being broken, but I think that works off the number of PMUs not the names of the PMUs, so it should be okay. Probably the only thing broken that matter is perf list when you have a BIG.little system with a520 and a720, this may be broken with say a a53 and a72 today as both of those suffix lengths are >2, but maybe they use the "armv8._pmuv3_0", "armv8._pmuv3_1", etc. naming convention. I suspect the >2 here: https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n80 would still work and be correct if it were >4. If that changes then this will also need to change: https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/Documentation/ABI/testing/sysfs-bus-event_source-devices?h=perf-tools-next#n12 Thanks, Ian > > Thanks, > Namhyung >
On 18/02/2025 10:33 pm, Ian Rogers wrote: > On Tue, Feb 18, 2025 at 2:19 PM Namhyung Kim <namhyung@kernel.org> wrote: >> >> On Tue, Feb 18, 2025 at 09:30:23AM +0000, James Clark wrote: >>> >>> >>> On 18/02/2025 12:41 am, Ian Rogers wrote: >>>> On Fri, Feb 14, 2025 at 2:02 AM James Clark <james.clark@linaro.org> wrote: >>>>> >>>>> >>>>> >>>>> On 14/02/2025 5:49 am, Yangyu Chen wrote: >>>>>> >>>>>> >>>>>>> On 14 Feb 2025, at 09:12, Namhyung Kim <namhyung@kernel.org> wrote: >>>>>>> >>>>>>> Hello, >>>>>>> >>>>>>> On Thu, Feb 13, 2025 at 11:11:01PM +0800, Yangyu Chen wrote: >>>>>>>> This patchset adds the perf JSON files for the Cortex-A720 and Cortex-A520 >>>>>>>> processors. Some events have been tested on Raxda Orion 6 with Cix P1 SoC >>>>>>>> (8xA720 + 4xA520) running mainline Kernel with ACPI mode. >>>>>>> >>>>>>> I'm curious how the name of PMUs look like. It is cortex_a720 (or a520)? >>>>>> >>>>>> The name of PMUs comes from Arm's documentation. I have included these >>>>>> links in each patch. >>>>>> >>>>>>> I remember there's a logic to check the length of hex digits at the end. >>>>>>> >>>>>> >>>>>> Could you provide more details about this? >>>>>> >>>>>>> Ian, are you ok with this? >>>>>>> >>>>> >>>>> I think they wouldn't be merged because they're core PMUs, so should be >>>>> fine? Even though they would otherwise be merged because they're more >>>>> than 3 hex digits. >>>> >>>> Do we know the PMU names? If they are cortex_a520 and cortex_a720 then >>> >>> It will be "armv9_cortex_a720" from this line: >>> >>> PMUV3_INIT_SIMPLE(armv9_cortex_a720) >> >> I see, thanks! >> >>> >>>> this comment at least reads a little stale: >>>> https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n76 >>>> ``` >>>> /* >>>> * There is a '_{num}' suffix. For decimal suffixes any length >>>> * will do, for hexadecimal ensure more than 2 hex digits so >>>> * that S390's cpum_cf PMU doesn't match. >>>> */ >>>> ``` >>>> James is right that core PMUs aren't put on the same list as uncore/other PMUs. >> >> Ok, then I guess we're good. > > I think you may be able to do things that look odd, like today the > "i915" PMU can be called just "i", I think the a520/a720 naming will > allow "armv9_cortex/cycles/" as an event name, then open it on two > PMUs if they are present. I assumed that was the intended behavior. It seems fairly useful to be able to open on ones with common prefixes. > We may only show one PMU in perf list as > that code I think assumes they're the same PMU as they only differ by > suffix: > https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n384 Yeah that is the case. I didn't realise it when looking at the previous fixes to keep the suffixes in perf stat output. > I can imagine aggregation possibly being broken, but I think that > works off the number of PMUs not the names of the PMUs, so it should > be okay. Probably the only thing broken that matter is perf list when > you have a BIG.little system with a520 and a720, this may be broken > with say a a53 and a72 today as both of those suffix lengths are >2, > but maybe they use the "armv8._pmuv3_0", "armv8._pmuv3_1", etc. naming > convention. I suspect the >2 here: Also the case for a53 and a72 right now. Even "perf list --unit armv8_cortex_a57" doesn't work because we deduplicate before filtering. Adding -v fixes it though because that disables deduplication. Perhaps we can change it to disable it with the --unit argument? > https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n80 > would still work and be correct if it were >4. If that changes then > this will also need to change: > https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/Documentation/ABI/testing/sysfs-bus-event_source-devices?h=perf-tools-next#n12 That could be an easy fix. If >4 is enough to still get rid of all the uncore duplicates I can make the change? > > Thanks, > Ian > >> >> Thanks, >> Namhyung >>
On Wed, Feb 19, 2025 at 7:25 AM James Clark <james.clark@linaro.org> wrote: > > > > On 18/02/2025 10:33 pm, Ian Rogers wrote: > > On Tue, Feb 18, 2025 at 2:19 PM Namhyung Kim <namhyung@kernel.org> wrote: > >> > >> On Tue, Feb 18, 2025 at 09:30:23AM +0000, James Clark wrote: > >>> > >>> > >>> On 18/02/2025 12:41 am, Ian Rogers wrote: > >>>> On Fri, Feb 14, 2025 at 2:02 AM James Clark <james.clark@linaro.org> wrote: > >>>>> > >>>>> > >>>>> > >>>>> On 14/02/2025 5:49 am, Yangyu Chen wrote: > >>>>>> > >>>>>> > >>>>>>> On 14 Feb 2025, at 09:12, Namhyung Kim <namhyung@kernel.org> wrote: > >>>>>>> > >>>>>>> Hello, > >>>>>>> > >>>>>>> On Thu, Feb 13, 2025 at 11:11:01PM +0800, Yangyu Chen wrote: > >>>>>>>> This patchset adds the perf JSON files for the Cortex-A720 and Cortex-A520 > >>>>>>>> processors. Some events have been tested on Raxda Orion 6 with Cix P1 SoC > >>>>>>>> (8xA720 + 4xA520) running mainline Kernel with ACPI mode. > >>>>>>> > >>>>>>> I'm curious how the name of PMUs look like. It is cortex_a720 (or a520)? > >>>>>> > >>>>>> The name of PMUs comes from Arm's documentation. I have included these > >>>>>> links in each patch. > >>>>>> > >>>>>>> I remember there's a logic to check the length of hex digits at the end. > >>>>>>> > >>>>>> > >>>>>> Could you provide more details about this? > >>>>>> > >>>>>>> Ian, are you ok with this? > >>>>>>> > >>>>> > >>>>> I think they wouldn't be merged because they're core PMUs, so should be > >>>>> fine? Even though they would otherwise be merged because they're more > >>>>> than 3 hex digits. > >>>> > >>>> Do we know the PMU names? If they are cortex_a520 and cortex_a720 then > >>> > >>> It will be "armv9_cortex_a720" from this line: > >>> > >>> PMUV3_INIT_SIMPLE(armv9_cortex_a720) > >> > >> I see, thanks! > >> > >>> > >>>> this comment at least reads a little stale: > >>>> https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n76 > >>>> ``` > >>>> /* > >>>> * There is a '_{num}' suffix. For decimal suffixes any length > >>>> * will do, for hexadecimal ensure more than 2 hex digits so > >>>> * that S390's cpum_cf PMU doesn't match. > >>>> */ > >>>> ``` > >>>> James is right that core PMUs aren't put on the same list as uncore/other PMUs. > >> > >> Ok, then I guess we're good. > > > > I think you may be able to do things that look odd, like today the > > "i915" PMU can be called just "i", I think the a520/a720 naming will > > allow "armv9_cortex/cycles/" as an event name, then open it on two > > PMUs if they are present. > > I assumed that was the intended behavior. It seems fairly useful to be > able to open on ones with common prefixes. > > > We may only show one PMU in perf list as > > that code I think assumes they're the same PMU as they only differ by > > suffix: > > https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n384 > > Yeah that is the case. I didn't realise it when looking at the previous > fixes to keep the suffixes in perf stat output. > > > I can imagine aggregation possibly being broken, but I think that > > works off the number of PMUs not the names of the PMUs, so it should > > be okay. Probably the only thing broken that matter is perf list when > > you have a BIG.little system with a520 and a720, this may be broken > > with say a a53 and a72 today as both of those suffix lengths are >2, > > but maybe they use the "armv8._pmuv3_0", "armv8._pmuv3_1", etc. naming > > convention. I suspect the >2 here: > > Also the case for a53 and a72 right now. Even "perf list --unit > armv8_cortex_a57" doesn't work because we deduplicate before filtering. > Adding -v fixes it though because that disables deduplication. Perhaps > we can change it to disable it with the --unit argument? > > > https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n80 > > would still work and be correct if it were >4. If that changes then > > this will also need to change: > > https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/Documentation/ABI/testing/sysfs-bus-event_source-devices?h=perf-tools-next#n12 > > That could be an easy fix. If >4 is enough to still get rid of all the > uncore duplicates I can make the change? The change would be great. I think it is sufficient and doesn't break the suffix: https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/drivers/perf/arm_dmc620_pmu.c?h=perf-tools-next#n710 https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/drivers/perf/arm_smmuv3_pmu.c?h=perf-tools-next#n921 https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/drivers/perf/marvell_cn10k_ddr_pmu.c?h=perf-tools-next#n1062 it is hard to tell as it is going to depend on the memory addresses placed in the PMU names. Perhaps you can clear this up and add zero padding in the drivers if the suffix is <=4 ? No documentation here: https://www.kernel.org/doc/Documentation/admin-guide/perf/mrvl-odyssey-ddr-pmu.rst On a test machine I see in /sys/devices : .. arm_dmc620_10008c400 .. on a different one I see: .. smmuv3_pmcg_20528a2 .. so >4 but this is an ARM specific issue as far as I can tell, so you'd be better placed to judge correctness than me. Thanks, Ian > > > > Thanks, > > Ian > > > >> > >> Thanks, > >> Namhyung > >> >
> On 19 Feb 2025, at 06:33, Ian Rogers <irogers@google.com> wrote: > > On Tue, Feb 18, 2025 at 2:19 PM Namhyung Kim <namhyung@kernel.org> wrote: >> >> On Tue, Feb 18, 2025 at 09:30:23AM +0000, James Clark wrote: >>> >>> >>> On 18/02/2025 12:41 am, Ian Rogers wrote: >>>> On Fri, Feb 14, 2025 at 2:02 AM James Clark <james.clark@linaro.org> wrote: >>>>> >>>>> >>>>> >>>>> On 14/02/2025 5:49 am, Yangyu Chen wrote: >>>>>> >>>>>> >>>>>>> On 14 Feb 2025, at 09:12, Namhyung Kim <namhyung@kernel.org> wrote: >>>>>>> >>>>>>> Hello, >>>>>>> >>>>>>> On Thu, Feb 13, 2025 at 11:11:01PM +0800, Yangyu Chen wrote: >>>>>>>> This patchset adds the perf JSON files for the Cortex-A720 and Cortex-A520 >>>>>>>> processors. Some events have been tested on Raxda Orion 6 with Cix P1 SoC >>>>>>>> (8xA720 + 4xA520) running mainline Kernel with ACPI mode. >>>>>>> >>>>>>> I'm curious how the name of PMUs look like. It is cortex_a720 (or a520)? >>>>>> >>>>>> The name of PMUs comes from Arm's documentation. I have included these >>>>>> links in each patch. >>>>>> >>>>>>> I remember there's a logic to check the length of hex digits at the end. >>>>>>> >>>>>> >>>>>> Could you provide more details about this? >>>>>> >>>>>>> Ian, are you ok with this? >>>>>>> >>>>> >>>>> I think they wouldn't be merged because they're core PMUs, so should be >>>>> fine? Even though they would otherwise be merged because they're more >>>>> than 3 hex digits. >>>> >>>> Do we know the PMU names? If they are cortex_a520 and cortex_a720 then >>> >>> It will be "armv9_cortex_a720" from this line: >>> >>> PMUV3_INIT_SIMPLE(armv9_cortex_a720) >> >> I see, thanks! >> >>> >>>> this comment at least reads a little stale: >>>> https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n76 >>>> ``` >>>> /* >>>> * There is a '_{num}' suffix. For decimal suffixes any length >>>> * will do, for hexadecimal ensure more than 2 hex digits so >>>> * that S390's cpum_cf PMU doesn't match. >>>> */ >>>> ``` >>>> James is right that core PMUs aren't put on the same list as uncore/other PMUs. >> >> Ok, then I guess we're good. > > I think you may be able to do things that look odd, like today the > "i915" PMU can be called just "i", I think the a520/a720 naming will > allow "armv9_cortex/cycles/" as an event name, then open it on two > PMUs if they are present. We may only show one PMU in perf list as > that code I think assumes they're the same PMU as they only differ by > suffix: > https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n384 > I can imagine aggregation possibly being broken, but I think that > works off the number of PMUs not the names of the PMUs, so it should > be okay. Probably the only thing broken that matter is perf list when > you have a BIG.little system with a520 and a720, this may be broken > with say a a53 and a72 today as both of those suffix lengths are >2, > but maybe they use the "armv8._pmuv3_0", "armv8._pmuv3_1", etc. naming > convention. I suspect the >2 here: > https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n80 > would still work and be correct if it were >4. If that changes then > this will also need to change: > https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/Documentation/ABI/testing/sysfs-bus-event_source-devices?h=perf-tools-next#n12 > > Thanks, > Ian > On my system, the names of PMUs are `armv8_pmuv3_0` and `armv8_pmuv3_1`: ``` $ ls /sys/bus/event_source/devices/ armv8_pmuv3_0 armv8_pmuv3_1 breakpoint kprobe software tracepoint uprobe ``` I searched for ACPI DSDT on my platform, but there's no mention of a720 or a520. I haven't delved into the PMU kernel driver yet. Additionally, there's a more significant problem for aarch64 BIG.little platforms when two or more types of cores don't have the same PMUs. The perf list can only display the core PMUs on core0 unless we use the PERF_CPUID env to override it. This is because perf will only probe the first MIDR here: https://github.com/torvalds/linux/blob/87a132e73910e8689902aed7f2fc229d6908383b/tools/perf/arch/arm64/util/header.c#L60 However, I think this doesn't block this patch for adding events and metrics? Thanks, Yangyu Chen >> >> Thanks, >> Namhyung
On 20/02/2025 3:33 am, Yangyu Chen wrote: > > >> On 19 Feb 2025, at 06:33, Ian Rogers <irogers@google.com> wrote: >> >> On Tue, Feb 18, 2025 at 2:19 PM Namhyung Kim <namhyung@kernel.org <mailto:namhyung@kernel.org>> wrote: >>> >>> On Tue, Feb 18, 2025 at 09:30:23AM +0000, James Clark wrote: >>>> >>>> >>>> On 18/02/2025 12:41 am, Ian Rogers wrote: >>>>> On Fri, Feb 14, 2025 at 2:02 AM James Clark <james.clark@linaro.org> wrote: >>>>>> >>>>>> >>>>>> >>>>>> On 14/02/2025 5:49 am, Yangyu Chen wrote: >>>>>>> >>>>>>> >>>>>>>> On 14 Feb 2025, at 09:12, Namhyung Kim <namhyung@kernel.org> wrote: >>>>>>>> >>>>>>>> Hello, >>>>>>>> >>>>>>>> On Thu, Feb 13, 2025 at 11:11:01PM +0800, Yangyu Chen wrote: >>>>>>>>> This patchset adds the perf JSON files for the Cortex-A720 and Cortex-A520 >>>>>>>>> processors. Some events have been tested on Raxda Orion 6 with Cix P1 SoC >>>>>>>>> (8xA720 + 4xA520) running mainline Kernel with ACPI mode. >>>>>>>> >>>>>>>> I'm curious how the name of PMUs look like. It is cortex_a720 (or a520)? >>>>>>> >>>>>>> The name of PMUs comes from Arm's documentation. I have included these >>>>>>> links in each patch. >>>>>>> >>>>>>>> I remember there's a logic to check the length of hex digits at the end. >>>>>>>> >>>>>>> >>>>>>> Could you provide more details about this? >>>>>>> >>>>>>>> Ian, are you ok with this? >>>>>>>> >>>>>> >>>>>> I think they wouldn't be merged because they're core PMUs, so should be >>>>>> fine? Even though they would otherwise be merged because they're more >>>>>> than 3 hex digits. >>>>> >>>>> Do we know the PMU names? If they are cortex_a520 and cortex_a720 then >>>> >>>> It will be "armv9_cortex_a720" from this line: >>>> >>>> PMUV3_INIT_SIMPLE(armv9_cortex_a720) >>> >>> I see, thanks! >>> >>>> >>>>> this comment at least reads a little stale: >>>>> https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n76 >>>>> ``` >>>>> /* >>>>> * There is a '_{num}' suffix. For decimal suffixes any length >>>>> * will do, for hexadecimal ensure more than 2 hex digits so >>>>> * that S390's cpum_cf PMU doesn't match. >>>>> */ >>>>> ``` >>>>> James is right that core PMUs aren't put on the same list as uncore/other PMUs. >>> >>> Ok, then I guess we're good. >> >> I think you may be able to do things that look odd, like today the >> "i915" PMU can be called just "i", I think the a520/a720 naming will >> allow "armv9_cortex/cycles/" as an event name, then open it on two >> PMUs if they are present. We may only show one PMU in perf list as >> that code I think assumes they're the same PMU as they only differ by >> suffix: >> https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n384 >> I can imagine aggregation possibly being broken, but I think that >> works off the number of PMUs not the names of the PMUs, so it should >> be okay. Probably the only thing broken that matter is perf list when >> you have a BIG.little system with a520 and a720, this may be broken >> with say a a53 and a72 today as both of those suffix lengths are >2, >> but maybe they use the "armv8._pmuv3_0", "armv8._pmuv3_1", etc. naming >> convention. I suspect the >2 here: >> https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmus.c?h=perf-tools-next#n80 >> would still work and be correct if it were >4. If that changes then >> this will also need to change: >> https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/Documentation/ABI/testing/sysfs-bus-event_source-devices?h=perf-tools-next#n12 >> >> Thanks, >> Ian >> > > On my system, the names of PMUs are `armv8_pmuv3_0` and > `armv8_pmuv3_1`: > > ``` > $ ls /sys/bus/event_source/devices/ > armv8_pmuv3_0 armv8_pmuv3_1 breakpoint kprobe software tracepoint uprobe > ``` > > I searched for ACPI DSDT on my platform, but there's no mention of > a720 or a520. I haven't delved into the PMU kernel driver yet. Ah yeah, with ACPI you get those names instead. > > Additionally, there's a more significant problem for aarch64 > BIG.little platforms when two or more types of cores don't have the > same PMUs. The perf list can only display the core PMUs on core0 > unless we use the PERF_CPUID env to override it. This is because > perf will only probe the first MIDR here: > https://github.com/torvalds/linux/blob/87a132e73910e8689902aed7f2fc229d6908383b/tools/perf/arch/arm64/util/header.c#L60 > > However, I think this doesn't block this patch for adding events and metrics? > > > Thanks, > Yangyu Chen > I don't think that's an issue because events are listed per PMU rather than per CPU and that MIDR function does take a CPU struct. From my testing the only thing stopping all PMUs from being listed was the numeric suffix de-duplication. Either way, no, it shouldn't affect your patch. But I'm also looking into Ian's suggestion to improve it anyway. >>> >>> Thanks, >>> Namhyung > >