| Message ID | 20250215013636.1214612-16-seanjc@google.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | x86/pmu: Fixes and improvements | expand |
On 2/15/2025 9:36 AM, Sean Christopherson wrote: > From: Dapeng Mi <dapeng1.mi@linux.intel.com> > > For these legacy Intel CPUs without clflush/clflushopt support, there is > on way to force to trigger a LLC miss and the measured llc misses is a typo: on -> no > possible to be 0. Thus adjust the lower boundary of llc-misses event to > 0 to avoid possible false positive. > > Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> > Signed-off-by: Sean Christopherson <seanjc@google.com> > --- > x86/pmu.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/x86/pmu.c b/x86/pmu.c > index 97c05177..1fc94f26 100644 > --- a/x86/pmu.c > +++ b/x86/pmu.c > @@ -81,6 +81,7 @@ struct pmu_event { > enum { > INTEL_INSTRUCTIONS_IDX = 1, > INTEL_REF_CYCLES_IDX = 2, > + INTEL_LLC_MISSES_IDX = 4, > INTEL_BRANCHES_IDX = 5, > }; > > @@ -889,6 +890,15 @@ int main(int ac, char **av) > gp_events_size = sizeof(intel_gp_events)/sizeof(intel_gp_events[0]); > instruction_idx = INTEL_INSTRUCTIONS_IDX; > branch_idx = INTEL_BRANCHES_IDX; > + > + /* > + * For legacy Intel CPUS without clflush/clflushopt support, > + * there is no way to force to trigger a LLC miss, thus set > + * the minimum value to 0 to avoid false positives. > + */ > + if (!this_cpu_has(X86_FEATURE_CLFLUSH)) > + gp_events[INTEL_LLC_MISSES_IDX].min = 0; > + > report_prefix_push("Intel"); > set_ref_cycle_expectations(); > } else {
diff --git a/x86/pmu.c b/x86/pmu.c index 97c05177..1fc94f26 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -81,6 +81,7 @@ struct pmu_event { enum { INTEL_INSTRUCTIONS_IDX = 1, INTEL_REF_CYCLES_IDX = 2, + INTEL_LLC_MISSES_IDX = 4, INTEL_BRANCHES_IDX = 5, }; @@ -889,6 +890,15 @@ int main(int ac, char **av) gp_events_size = sizeof(intel_gp_events)/sizeof(intel_gp_events[0]); instruction_idx = INTEL_INSTRUCTIONS_IDX; branch_idx = INTEL_BRANCHES_IDX; + + /* + * For legacy Intel CPUS without clflush/clflushopt support, + * there is no way to force to trigger a LLC miss, thus set + * the minimum value to 0 to avoid false positives. + */ + if (!this_cpu_has(X86_FEATURE_CLFLUSH)) + gp_events[INTEL_LLC_MISSES_IDX].min = 0; + report_prefix_push("Intel"); set_ref_cycle_expectations(); } else {