| Message ID | 20250219104435.1525-2-thorsten.blum@linux.dev (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [RESEND] clk: socfpga: stratix10: Optimize local variables | expand |
On 2/19/25 04:44, Thorsten Blum wrote: > Since readl() returns a u32, the local variable reg can also have the > data type u32. Furthermore, mdiv and refdiv are derived from reg and can > also be a u32. > > Since do_div() casts the divisor to u32 anyway, changing the data type > of refdiv to u32 removes the following Coccinelle/coccicheck warning > reported by do_div.cocci: > > WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead > > Compile-tested only. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> > --- > drivers/clk/socfpga/clk-pll-s10.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > Applied! Thanks, Dinh
diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c index 1d82737befd3..a88c212bda12 100644 --- a/drivers/clk/socfpga/clk-pll-s10.c +++ b/drivers/clk/socfpga/clk-pll-s10.c @@ -83,9 +83,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, unsigned long parent_rate) { struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); - unsigned long mdiv; - unsigned long refdiv; - unsigned long reg; + u32 mdiv; + u32 refdiv; + u32 reg; unsigned long long vco_freq; /* read VCO1 reg for numerator and denominator */