| Message ID | 20250220061107.1718239-5-yschu@nuvoton.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for Nuvoton npcm845 i3c controller | expand |
On Thu, Feb 20, 2025 at 02:11:07PM +0800, Stanley Chu wrote: > From: Stanley Chu <yschu@nuvoton.com> > > I3C HW may generate an invalid SlvStart event when emitting a STOP. > If it is a true SlvStart, the MSTATUS state should be SLVREQ. Check ^^^ is? "should be" look like unconfirmed. > the MSTATUS state to ignore the false event. > > Signed-off-by: Stanley Chu <yschu@nuvoton.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> > --- > drivers/i3c/master/svc-i3c-master.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c > index 2140da3f5187..5861358eb9e5 100644 > --- a/drivers/i3c/master/svc-i3c-master.c > +++ b/drivers/i3c/master/svc-i3c-master.c > @@ -58,6 +58,7 @@ > #define SVC_I3C_MSTATUS 0x088 > #define SVC_I3C_MSTATUS_STATE(x) FIELD_GET(GENMASK(2, 0), (x)) > #define SVC_I3C_MSTATUS_STATE_DAA(x) (SVC_I3C_MSTATUS_STATE(x) == 5) > +#define SVC_I3C_MSTATUS_STATE_SLVREQ(x) (SVC_I3C_MSTATUS_STATE(x) == 1) > #define SVC_I3C_MSTATUS_STATE_IDLE(x) (SVC_I3C_MSTATUS_STATE(x) == 0) > #define SVC_I3C_MSTATUS_BETWEEN(x) FIELD_GET(BIT(4), (x)) > #define SVC_I3C_MSTATUS_NACKED(x) FIELD_GET(BIT(5), (x)) > @@ -589,6 +590,11 @@ static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id) > /* Clear the interrupt status */ > writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS); > > + /* Ignore the false event */ > + if ((master->quirks & SVC_I3C_QUIRK_FALSE_SLVSTART) && > + !SVC_I3C_MSTATUS_STATE_SLVREQ(active)) > + return IRQ_HANDLED; > + > svc_i3c_master_disable_interrupts(master); > > /* Handle the interrupt in a non atomic context */ > -- > 2.34.1 >
diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c index 2140da3f5187..5861358eb9e5 100644 --- a/drivers/i3c/master/svc-i3c-master.c +++ b/drivers/i3c/master/svc-i3c-master.c @@ -58,6 +58,7 @@ #define SVC_I3C_MSTATUS 0x088 #define SVC_I3C_MSTATUS_STATE(x) FIELD_GET(GENMASK(2, 0), (x)) #define SVC_I3C_MSTATUS_STATE_DAA(x) (SVC_I3C_MSTATUS_STATE(x) == 5) +#define SVC_I3C_MSTATUS_STATE_SLVREQ(x) (SVC_I3C_MSTATUS_STATE(x) == 1) #define SVC_I3C_MSTATUS_STATE_IDLE(x) (SVC_I3C_MSTATUS_STATE(x) == 0) #define SVC_I3C_MSTATUS_BETWEEN(x) FIELD_GET(BIT(4), (x)) #define SVC_I3C_MSTATUS_NACKED(x) FIELD_GET(BIT(5), (x)) @@ -589,6 +590,11 @@ static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id) /* Clear the interrupt status */ writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS); + /* Ignore the false event */ + if ((master->quirks & SVC_I3C_QUIRK_FALSE_SLVSTART) && + !SVC_I3C_MSTATUS_STATE_SLVREQ(active)) + return IRQ_HANDLED; + svc_i3c_master_disable_interrupts(master); /* Handle the interrupt in a non atomic context */