[00/14] Add support for AD4080 ADC

Message

Antoniu Miclaus Feb. 20, 2025, 1:54 p.m. UTC

The AD4080 is a high-speed, low noise, low distortion, 20-bit, Easy
Drive, successive approximation register (SAR) analog-to-digital
converter (ADC). Maintaining high performance (signal-to-noise and
distortion (SINAD) ratio > 90 dBFS) at signal frequencies in excess
of 1 MHz enables the AD4080 to service a wide variety of precision,
wide bandwidth data acquisition applications. Simplification of the
input anti-alias filter design can be accomplished by applying over-
sampling along with the integrated digital filtering and decimation to
reduce noise and lower the output data rate for applications that do
not require the lowest latency of the AD4080.

Antoniu Miclaus (14):
  iio: backend: add support for filter config
  iio: backend: add support for sync process
  iio: backend: add support for self sync
  iio: backend: add support for sync status
  iio: backend: add support for number of lanes
  dt-bindings: iio: adc: add ad408x axi variant
  iio: adc: adi-axi-adc: add filter enable/disable
  iio: adc: adi-axi-adc: add bitslip enable/disable
  iio: adc: adi-axi-adc: add self sync support
  iio: adc: adi-axi-adc: add sync status
  iio: adc: adi-axi-adc: add num lanes support
  dt-bindings: iio: adc: add ad4080
  iio: adc: ad4080: add driver support
  Documentation: ABI: testing: ad4080 docs

 .../ABI/testing/sysfs-bus-iio-adc-ad4080      |  55 ++
 .../bindings/iio/adc/adi,ad4080.yaml          |  92 +++
 .../bindings/iio/adc/adi,axi-adc.yaml         |   2 +
 drivers/iio/adc/Kconfig                       |  15 +
 drivers/iio/adc/Makefile                      |   1 +
 drivers/iio/adc/ad4080.c                      | 768 ++++++++++++++++++
 drivers/iio/adc/adi-axi-adc.c                 | 115 +++
 drivers/iio/industrialio-backend.c            | 113 +++
 include/linux/iio/backend.h                   |  24 +
 9 files changed, 1185 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-adc-ad4080
 create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml
 create mode 100644 drivers/iio/adc/ad4080.c

Comments

David Lechner Feb. 20, 2025, 8:12 p.m. UTC | #1

On 2/20/25 7:54 AM, Antoniu Miclaus wrote:
> The AD4080 is a high-speed, low noise, low distortion, 20-bit, Easy
> Drive, successive approximation register (SAR) analog-to-digital
> converter (ADC). Maintaining high performance (signal-to-noise and
> distortion (SINAD) ratio > 90 dBFS) at signal frequencies in excess
> of 1 MHz enables the AD4080 to service a wide variety of precision,
> wide bandwidth data acquisition applications. Simplification of the
> input anti-alias filter design can be accomplished by applying over-
> sampling along with the integrated digital filtering and decimation to
> reduce noise and lower the output data rate for applications that do
> not require the lowest latency of the AD4080.
> 
It looks like this was just copied from the datasheet, so not useful
at all for a cover letter. We can read it in the datasheet.

Instead, please spend some time to explain the interesting and
unusual things about this driver that will help reviewers understand
*why* you are doing what you are doing. This is a very complex driver!

In particular, on this one, the documentation on the FPGA IP block isn't
very detailed. So it will be very helpful to know more about how all of
the sync stuff is supposed to work and what kind of filtering is the
FPGA doing in addition to the filtering done in the ADC chip.

Jonathan Cameron Feb. 22, 2025, 4:56 p.m. UTC | #2

On Thu, 20 Feb 2025 14:12:06 -0600
David Lechner <[e-mail]> wrote:

> On 2/20/25 7:54 AM, Antoniu Miclaus wrote:
> > The AD4080 is a high-speed, low noise, low distortion, 20-bit, Easy
> > Drive, successive approximation register (SAR) analog-to-digital
> > converter (ADC). Maintaining high performance (signal-to-noise and
> > distortion (SINAD) ratio > 90 dBFS) at signal frequencies in excess
> > of 1 MHz enables the AD4080 to service a wide variety of precision,
> > wide bandwidth data acquisition applications. Simplification of the
> > input anti-alias filter design can be accomplished by applying over-
> > sampling along with the integrated digital filtering and decimation to
> > reduce noise and lower the output data rate for applications that do
> > not require the lowest latency of the AD4080.
> >   
> It looks like this was just copied from the datasheet, so not useful
> at all for a cover letter. We can read it in the datasheet.
> 
> Instead, please spend some time to explain the interesting and
> unusual things about this driver that will help reviewers understand
> *why* you are doing what you are doing. This is a very complex driver!
> 
> In particular, on this one, the documentation on the FPGA IP block isn't
> very detailed. So it will be very helpful to know more about how all of
> the sync stuff is supposed to work and what kind of filtering is the
> FPGA doing in addition to the filtering done in the ADC chip.
> 
> 
> 
> 

This is a somewhat unusual device. I think a nice file with diagrams
etc under Documentation would also be good to have!

Jonathan