| Message ID | ad5bf4dde8ab637e9c5c24d7391ad36c7aafd8b7.1738869208.git.babu.moger@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/i386: Update EPYC CPU models for Cache property, RAS, SVM feature and add EPYC-Turin CPU model | expand |
On Thu, Feb 06, 2025 at 01:28:37PM -0600, Babu Moger wrote: > Date: Thu, 6 Feb 2025 13:28:37 -0600 > From: Babu Moger <babu.moger@amd.com> > Subject: [PATCH v5 4/6] target/i386: Add feature that indicates WRMSR to > BASE reg is non-serializing > X-Mailer: git-send-email 2.34.1 > > Add the CPUID bit indicates that a WRMSR to MSR_FS_BASE, MSR_GS_BASE, or > MSR_KERNEL_GS_BASE is non-serializing. > > CPUID_Fn80000021_EAX > Bit Feature description > 1 FsGsKernelGsBaseNonSerializing. > WRMSR to FS_BASE, GS_BASE and KernelGSbase are non-serializing. > > Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip > Signed-off-by: Babu Moger <babu.moger@amd.com> > Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru> > --- > target/i386/cpu.c | 2 +- > target/i386/cpu.h | 2 ++ > 2 files changed, 3 insertions(+), 1 deletion(-) Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Hi Zhao, On 2/20/2025 6:00 AM, Zhao Liu wrote: > On Thu, Feb 06, 2025 at 01:28:37PM -0600, Babu Moger wrote: >> Date: Thu, 6 Feb 2025 13:28:37 -0600 >> From: Babu Moger <babu.moger@amd.com> >> Subject: [PATCH v5 4/6] target/i386: Add feature that indicates WRMSR to >> BASE reg is non-serializing >> X-Mailer: git-send-email 2.34.1 >> >> Add the CPUID bit indicates that a WRMSR to MSR_FS_BASE, MSR_GS_BASE, or >> MSR_KERNEL_GS_BASE is non-serializing. >> >> CPUID_Fn80000021_EAX >> Bit Feature description >> 1 FsGsKernelGsBaseNonSerializing. >> WRMSR to FS_BASE, GS_BASE and KernelGSbase are non-serializing. >> >> Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip >> Signed-off-by: Babu Moger <babu.moger@amd.com> >> Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru> >> --- >> target/i386/cpu.c | 2 +- >> target/i386/cpu.h | 2 ++ >> 2 files changed, 3 insertions(+), 1 deletion(-) > > Reviewed-by: Zhao Liu <zhao1.liu@intel.com> > Thank you, Babu
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7d18557877..710b862eec 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1234,7 +1234,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { [FEAT_8000_0021_EAX] = { .type = CPUID_FEATURE_WORD, .feat_names = { - "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, + "no-nested-data-bp", "fs-gs-base-ns", "lfence-always-serializing", NULL, NULL, NULL, "null-sel-clr-base", NULL, "auto-ibrs", NULL, NULL, NULL, NULL, NULL, NULL, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index c67b42d34f..968b4fd99b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1074,6 +1074,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); /* Processor ignores nested data breakpoints */ #define CPUID_8000_0021_EAX_NO_NESTED_DATA_BP (1U << 0) +/* WRMSR to FS_BASE, GS_BASE, or KERNEL_GS_BASE is non-serializing */ +#define CPUID_8000_0021_EAX_FS_GS_BASE_NS (1U << 1) /* LFENCE is always serializing */ #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2) /* Null Selector Clears Base */
Add the CPUID bit indicates that a WRMSR to MSR_FS_BASE, MSR_GS_BASE, or MSR_KERNEL_GS_BASE is non-serializing. CPUID_Fn80000021_EAX Bit Feature description 1 FsGsKernelGsBaseNonSerializing. WRMSR to FS_BASE, GS_BASE and KernelGSbase are non-serializing. Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip Signed-off-by: Babu Moger <babu.moger@amd.com> Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru> --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-)