| Message ID | 20250221063528.1810007-3-yschu@nuvoton.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for Nuvoton npcm845 i3c controller | expand |
Hi Stanley,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master v6.14-rc3 next-20250221]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Stanley-Chu/dt-bindings-i3c-silvaco-Add-npcm845-compatible-string/20250221-143909
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20250221063528.1810007-3-yschu%40nuvoton.com
patch subject: [PATCH v3 2/4] i3c: master: svc: Add support for Nuvoton npcm845 i3c
config: arm-randconfig-003-20250222 (https://download.01.org/0day-ci/archive/20250222/202502221511.0BCyUyEU-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250222/202502221511.0BCyUyEU-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202502221511.0BCyUyEU-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/i3c/master/svc-i3c-master.c:240: warning: Function parameter or struct member 'drvdata' not described in 'svc_i3c_master'
vim +240 drivers/i3c/master/svc-i3c-master.c
28c82e7b13d49b1 Stanley Chu 2025-02-21 180
dd3c52846d5954a Miquel Raynal 2021-01-21 181 /**
dd3c52846d5954a Miquel Raynal 2021-01-21 182 * struct svc_i3c_master - Silvaco I3C Master structure
dd3c52846d5954a Miquel Raynal 2021-01-21 183 * @base: I3C master controller
dd3c52846d5954a Miquel Raynal 2021-01-21 184 * @dev: Corresponding device
dd3c52846d5954a Miquel Raynal 2021-01-21 185 * @regs: Memory mapping
5496eac6ad7428f Miquel Raynal 2023-08-17 186 * @saved_regs: Volatile values for PM operations
dd3c52846d5954a Miquel Raynal 2021-01-21 187 * @free_slots: Bit array of available slots
dd3c52846d5954a Miquel Raynal 2021-01-21 188 * @addrs: Array containing the dynamic addresses of each attached device
dd3c52846d5954a Miquel Raynal 2021-01-21 189 * @descs: Array of descriptors, one per attached device
dd3c52846d5954a Miquel Raynal 2021-01-21 190 * @hj_work: Hot-join work
dd3c52846d5954a Miquel Raynal 2021-01-21 191 * @ibi_work: IBI work
dd3c52846d5954a Miquel Raynal 2021-01-21 192 * @irq: Main interrupt
dd3c52846d5954a Miquel Raynal 2021-01-21 193 * @pclk: System clock
dd3c52846d5954a Miquel Raynal 2021-01-21 194 * @fclk: Fast clock (bus)
dd3c52846d5954a Miquel Raynal 2021-01-21 195 * @sclk: Slow clock (other events)
dd3c52846d5954a Miquel Raynal 2021-01-21 196 * @xferqueue: Transfer queue structure
dd3c52846d5954a Miquel Raynal 2021-01-21 197 * @xferqueue.list: List member
dd3c52846d5954a Miquel Raynal 2021-01-21 198 * @xferqueue.cur: Current ongoing transfer
dd3c52846d5954a Miquel Raynal 2021-01-21 199 * @xferqueue.lock: Queue lock
dd3c52846d5954a Miquel Raynal 2021-01-21 200 * @ibi: IBI structure
dd3c52846d5954a Miquel Raynal 2021-01-21 201 * @ibi.num_slots: Number of slots available in @ibi.slots
dd3c52846d5954a Miquel Raynal 2021-01-21 202 * @ibi.slots: Available IBI slots
dd3c52846d5954a Miquel Raynal 2021-01-21 203 * @ibi.tbq_slot: To be queued IBI slot
dd3c52846d5954a Miquel Raynal 2021-01-21 204 * @ibi.lock: IBI lock
6bf3fc268183816 Frank Li 2023-10-23 205 * @lock: Transfer lock, protect between IBI work thread and callbacks from master
05b26c31a4859af Frank Li 2023-12-01 206 * @enabled_events: Bit masks for enable events (IBI, HotJoin).
20ade67bb1645f5 Carlos Song 2024-09-10 207 * @mctrl_config: Configuration value in SVC_I3C_MCTRL for setting speed back.
dd3c52846d5954a Miquel Raynal 2021-01-21 208 */
dd3c52846d5954a Miquel Raynal 2021-01-21 209 struct svc_i3c_master {
dd3c52846d5954a Miquel Raynal 2021-01-21 210 struct i3c_master_controller base;
dd3c52846d5954a Miquel Raynal 2021-01-21 211 struct device *dev;
dd3c52846d5954a Miquel Raynal 2021-01-21 212 void __iomem *regs;
1c5ee2a77b1bacd Clark Wang 2023-05-17 213 struct svc_i3c_regs_save saved_regs;
dd3c52846d5954a Miquel Raynal 2021-01-21 214 u32 free_slots;
dd3c52846d5954a Miquel Raynal 2021-01-21 215 u8 addrs[SVC_I3C_MAX_DEVS];
dd3c52846d5954a Miquel Raynal 2021-01-21 216 struct i3c_dev_desc *descs[SVC_I3C_MAX_DEVS];
dd3c52846d5954a Miquel Raynal 2021-01-21 217 struct work_struct hj_work;
dd3c52846d5954a Miquel Raynal 2021-01-21 218 struct work_struct ibi_work;
dd3c52846d5954a Miquel Raynal 2021-01-21 219 int irq;
dd3c52846d5954a Miquel Raynal 2021-01-21 220 struct clk *pclk;
dd3c52846d5954a Miquel Raynal 2021-01-21 221 struct clk *fclk;
dd3c52846d5954a Miquel Raynal 2021-01-21 222 struct clk *sclk;
dd3c52846d5954a Miquel Raynal 2021-01-21 223 struct {
dd3c52846d5954a Miquel Raynal 2021-01-21 224 struct list_head list;
dd3c52846d5954a Miquel Raynal 2021-01-21 225 struct svc_i3c_xfer *cur;
dd3c52846d5954a Miquel Raynal 2021-01-21 226 /* Prevent races between transfers */
dd3c52846d5954a Miquel Raynal 2021-01-21 227 spinlock_t lock;
dd3c52846d5954a Miquel Raynal 2021-01-21 228 } xferqueue;
dd3c52846d5954a Miquel Raynal 2021-01-21 229 struct {
dd3c52846d5954a Miquel Raynal 2021-01-21 230 unsigned int num_slots;
dd3c52846d5954a Miquel Raynal 2021-01-21 231 struct i3c_dev_desc **slots;
dd3c52846d5954a Miquel Raynal 2021-01-21 232 struct i3c_ibi_slot *tbq_slot;
dd3c52846d5954a Miquel Raynal 2021-01-21 233 /* Prevent races within IBI handlers */
dd3c52846d5954a Miquel Raynal 2021-01-21 234 spinlock_t lock;
dd3c52846d5954a Miquel Raynal 2021-01-21 235 } ibi;
6bf3fc268183816 Frank Li 2023-10-23 236 struct mutex lock;
28c82e7b13d49b1 Stanley Chu 2025-02-21 237 const struct svc_i3c_drvdata *drvdata;
25bc99be5fe5385 Frank Li 2024-11-01 238 u32 enabled_events;
20ade67bb1645f5 Carlos Song 2024-09-10 239 u32 mctrl_config;
dd3c52846d5954a Miquel Raynal 2021-01-21 @240 };
dd3c52846d5954a Miquel Raynal 2021-01-21 241
diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c index d6057d8c7dec..1e7e3e1f3d22 100644 --- a/drivers/i3c/master/svc-i3c-master.c +++ b/drivers/i3c/master/svc-i3c-master.c @@ -133,6 +133,22 @@ #define SVC_I3C_EVENT_IBI GENMASK(7, 0) #define SVC_I3C_EVENT_HOTJOIN BIT(31) +/* + * SVC_I3C_QUIRK_FIFO_EMPTY: + * I3C HW stalls the write transfer if the transmit FIFO becomes empty, + * when new data is written to FIFO, I3C HW resumes the transfer but + * the first transmitted data bit may have the wrong value. + * Workaround: + * Fill the FIFO in advance to prevent FIFO from becoming empty. + */ +#define SVC_I3C_QUIRK_FIFO_EMPTY BIT(0) +/* + * SVC_I3C_QUIRK_FLASE_SLVSTART: + * I3C HW may generate an invalid SlvStart event when emitting a STOP. + * If it is a true SlvStart, the MSTATUS state is SLVREQ. + */ +#define SVC_I3C_QUIRK_FALSE_SLVSTART BIT(1) + struct svc_i3c_cmd { u8 addr; bool rnw; @@ -158,6 +174,10 @@ struct svc_i3c_regs_save { u32 mdynaddr; }; +struct svc_i3c_drvdata { + u32 quirks; +}; + /** * struct svc_i3c_master - Silvaco I3C Master structure * @base: I3C master controller @@ -214,6 +234,7 @@ struct svc_i3c_master { spinlock_t lock; } ibi; struct mutex lock; + const struct svc_i3c_drvdata *drvdata; u32 enabled_events; u32 mctrl_config; }; @@ -230,6 +251,15 @@ struct svc_i3c_i2c_dev_data { struct i3c_generic_ibi_pool *ibi_pool; }; +const struct svc_i3c_drvdata npcm845_drvdata = { + .quirks = SVC_I3C_QUIRK_FIFO_EMPTY | SVC_I3C_QUIRK_FALSE_SLVSTART, +}; + +static inline bool svc_has_quirk(struct svc_i3c_master *master, u32 quirk) +{ + return (master->drvdata && (master->drvdata->quirks & quirk)); +} + static inline bool is_events_enabled(struct svc_i3c_master *master, u32 mask) { return !!(master->enabled_events & mask); @@ -1868,6 +1898,7 @@ static int svc_i3c_master_probe(struct platform_device *pdev) } platform_set_drvdata(pdev, master); + master->drvdata = of_device_get_match_data(dev); pm_runtime_set_autosuspend_delay(&pdev->dev, SVC_I3C_PM_TIMEOUT_MS); pm_runtime_use_autosuspend(&pdev->dev); @@ -1960,6 +1991,7 @@ static const struct dev_pm_ops svc_i3c_pm_ops = { static const struct of_device_id svc_i3c_master_of_match_tbl[] = { { .compatible = "silvaco,i3c-master-v1"}, + { .compatible = "nuvoton,npcm845-i3c", .data = &npcm845_drvdata }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, svc_i3c_master_of_match_tbl);